Synthesis for FPGAs with embedded memory blocks

ABSTRACT

Embedded memory blocks (EMBs) are used in modern field programmable gate arrays (FPGAs) for implementation of on-chip memories or specialized logic functions[1]. In this paper, we propose an integrated approach with structural clustering and functional decomposition to minimize the circuit area using EMBs while preserving the circuit delay. The structural clustering method is based on the concepts of Maximum Fanout Free Cone (MFFC)[5] and Maximum Fanout Free Subgraph (MFFS)[5]. In order to effectively use EMB in large clusters, single-output and multiple-output functional decompositions are used to decompose large clusters so that the encoding functions or base functions can be implemented by EMBs. It also considers multiple EMBs for individual large cluster so that better area reduction can be obtained. We have developed an algorithm called EMB_Syn that can be used as a postprocessing tool in the FPGA synthesis flow. MCNC benchmarks are used to test EMB_Syn on Altera's FLEX10K device family and the experimental results are compared with those by EMB_Pack[8] and SMAP[10]. When EMB_Syn is used as postmapping processing, it shows 45.06% and up to 5.23% improvements over EMB_Pack and SMAP, respectively, in terms of the covered area by EMBs.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

General Terms:
Design, Experimentation, Performance, Theory