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On the equivalence of pull-up transistor assignment in PLA folding and distribution graph
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Source Symposium on Applied Computing archive
Proceedings of the 1994 ACM symposium on Applied computing table of contents
Phoenix, Arizona, United States
Pages: 374 - 378  
Year of Publication: 1994
ISBN:0-89791-647-6
Author
Wing Ning Li  University of Arkansas
Sponsors
SIGAPL: ACM Special Interest Group on APL Programming Language
SIGCUE: ACM Special Interest Group on Computer Uses In Education
SIGICE: ACM Special Interest Group on Individual Computing Environment
SIGAPP: ACM Special Interest Group on Applied Computing
SIGBIO: ACM Special Interest Group on Biomedical Computing
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 4,   Downloads (12 Months): 8,   Citation Count: 0
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
C. DeMicheli and A. Sangiovanni-Vincentelli, "PLEAS- URE: A computer program for simple/multiple constrained/unconstrained folding of programmable logic arrays," Memo. 'UCB/ERL M$2/57, 1982, Univ. Calif., Berkeley, 1982.
 
2
J. R. Egan , C. L. Liu, Optimal bipartite folding of PLA, Proceedings of the 19th conference on Design automation, p.141-146, January 1982
 
3
G. Hachtel, A. Newton, and A. Sangiovanni-Vincentelli, "An algorithm for optimal PLA folding," IEEli 7'ran.v. (.'omputer-Airh,d Design, vo'l. CAD-t, pp. 63-77, Apr. 1982.
4
Akihiro Hashimoto , James Stevens, Wire routing by optimizing channel assignment within large apertures, Proceedings of the 8th workshop on Design automation, p.155-169, June 28-30, 1971, Atlantic City, New Jersey, United States  [doi>10.1145/800158.805069]
 
5
S. Hwang, R. Dutton, and T. Blank, "A best-first search algorithm for optirnal PLA folding," IEEE Tratzr. Computer-Aided Design, vol. CAD-5, pp. 433442, Jul. 1986.
 
6
W. Li and $. Satmi, "Pull-up transistor folding," IEEE Trans. Computer-Aided Design, vol. CAD-9, pp. 512- 521, May. 1990.
 
7
C. Lursinsap and D. Gajski, "A technique for pull-up transistor folding," I~EE Trar~. Computer-Aided Design, vol. CAD-7, pp. 887-896, Aug. 1988.
 
8
V. Raghavan, "On the equivalenee of maximum carctinality ma~ching m bipartite graphs and maximum flow in unit network," TR 87-.58, Computer Science department, University of Minnesota, December 1987.
 
9
I. Suwa , W. J. Kubitz, A computer-aided-design system for segmented-folded PLA macro-cells, Proceedings of the 18th conference on Design automation, p.398-405, June 29-July 01, 1981, Nashville, Tennessee, United States

INDEX TERMS

Primary Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Logic arrays

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)
  B.8 Performance and Reliability

  G. Mathematics of Computing
  G.2 DISCRETE MATHEMATICS


General Terms:
Design, Measurement, Performance, Theory, Verification

Collaborative Colleagues:
Wing Ning Li: colleagues

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