Efficient Exercising of Switching Elements in Nets of Identical Gates

ABSTRACT

The problem of finding a minimum number of patterns to exercise the logic elements of a combinational switching net is investigated. Throughout, the word “testing” refers to exercising of this kind; or, equivalently, to fault diagnosis where each line of the net can be directly observed. Any set of permanent faults can be selected to test against, examples of which range from “stuck-at” faults (allowing the most economical test) to “any possible fault” (requiring the most complete test). The method used depends upon exact structural analysis rather than upon search algorithms or random pattern generation. The types of results presented appear to be fundamentally new. In particular, the maximum number of patterns required to test any one of an infinite class of nets is frequently found to be finite and extremely small. For example, any nontrivial connected tree of 2-input nand gates can be tested for “any possible fault” by exactly five patterns—no more and no less. The method in brief: Given a set F of switching functions and a set of required inputs for each (collectively denoted T), a “testing” function is defined for each element of F for each positive integer r. If the lines of a net can be mapped to the domain of the testing functions P(T, r) so that the gates perform consistent with these functions, we say the net “accepts” P(T, r)—and then r patterns are sufficient to test the net for T. Only nets in which each logic element is intended to realize the same switching function are discussed here. Trees (nets without fanout) are studied first, and the conditions under which a tree of identical gates “accepts” a partial function on an arbitrary domain is established. Then the common symmetric switching functions are separately investigated to find for each a minimum value of r such that all trees composed solely of the function accept P(T, r) (for various T). In most cases, as in the example given, the number of patterns required to test any such tree is extremely low. The conditions under which all nets (nontrees included) accept a set of partial functions with arbitrary domain are then established. These conditions are rarely met in practice, even where F consists of a single function. However, many subclasses of nets can be identified which require only a few patterns at most (depending on the function and the class of faults selected). These subclasses often contain nets of arbitrary size and complexity, and frequently consist of exactly those nets for which a related graph can be “colored” (i.e., h-node colored for some particular h) in the classical graph-theoretic sense. For example, any net of 2-input nand gates can be tested by five patterns if one of its related graphs is 2-colorable and another one is 3-colorable (!). The detailed results and methods used to obtain them are summarized, and in conclusion coloring problems and test construction are commented upon.

REFERENCES

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INDEX TERMS

Primary Classification:
  G. Mathematics of Computing
  G.2 DISCRETE MATHEMATICS

Additional Classification:
  B. Hardware
  B.8 Performance and Reliability

General Terms:
Design, Measurement, Performance, Reliability, Theory, Verification