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VLSI design process
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Proceedings of the 1985 ACM thirteenth annual conference on Computer Science table of contents
New Orleans, Louisiana, United States
Pages: 74 - 78  
Year of Publication: 1985
ISBN:0-89791-150-4
Authors
Vishwani Agrawal  AT&T Bell Laboratories, Murray Hill, New Jersey
Samuel H. C. Poon  AT&T Bell Laboratories, Murray Hill, New Jersey
Sponsor
ACM: Association for Computing Machinery
Publisher
ACM  New York, NY, USA
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ABSTRACT

This paper presents a review of the computer-aided design of VLSI devices. For illustrative purposes, the design methodology is modeled as an idealized two-level process. In the first level, known as the functional level, the requirements of the device are converted into logic description and tests are generated. The second level consists of the physical design involving layout. In each level, our model represents the design as a feedback process with verification closing the loop on synthesis or layout. While the future design methodology might be closer to this idealization, today's design process differs significantly depending upon the specific design environment.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
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Collaborative Colleagues:
Vishwani Agrawal: colleagues
Samuel H. C. Poon: colleagues

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