Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	The structure of parallel Algorithms: H.T. Kung: CMU Internal Report CMU-CS-79-143: Aug 1979.
	2	Paul L. Mills, The design of bit-parallel systolic filter algorithms, Proceedings of the ACM 12th annual computer science conference on SIGCSE symposium, p.121-130, February 14-16, 1984, Philadelphia, Pennsylvania  [doi>10.1145/800014.808151]
	3	The Design of Bit-parallel Systolic Fileter Algorithms II: P.L. Mills: Proceedings of the 7th International Conference on Pattern Recognition, Montreal, Canada: June 1984.
	4	A Two's Complement Parallel Array Multiplication Algorithm: Baugh and Wooley: IEEE Transactions on Computer, vol C22 Number 1-2, pp1045-1047, Dec 1973
	5	A Bit Level Systolic Array Circuit for Matrix by Vector Multiplication: J.V McCanny and J.G McWhirter: IEE Part G, Electronic Circuits and Systems.
	6	The Relationship Between Word and Bit-Level Systolic Arrays as Applied to Matrix-Matrix Multiplication: J.V McCanny and K. W. Wood and J.G McWhirter:and C.J. Oliver: Real Time Signal Processing 4, San Diego, USA Aug 1983.
	7	The Design of Systolic Arrays for Finite Numerical Functions. PhD Thesis Cambridge University England 1984.

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