Resistance calculation from mask artwork data by finite element method

ABSTRACT

Traditional methods for resistance calculation suffer from some unfavourable features, that make them uncomfortable to use. Although requiring a lot of manual processing, they are rather inaccurate and often claim for severe artwork restrictions (e.g. orthogonal geometry)which conflict with the desire for most dense layouts. This paper describes a resistance calculation program called REX (Resistance Extractor), which is based on the well-known Finite Element Method (FEM). Highly felxible in use, it is able to process designed and parasitic resistors of any shape and material with adjustable precision. REX is part of the layout verification system ALAS, designed for mask artwork analysis of bipolar circuits.

REFERENCES

• 1: Erich Barke, A layout verification system for analog bipolar integrated circuits, Proceedings of the 20th conference on Design automation, p.353-359, June 27-29, 1983, Miami Beach, Florida, United States
• 2: Hall, R.M., s~stance Calculation for Thin Film Patterns", Thin Solid Films, Vol. ! (1967), pp. 277-295.
• 3: Ozak~, T., Yoshida, J., Kosaka, M., "PANAMAP-I: A Mask Pattern Analysis Program for IC/LS~ - Centerline Extraction and Resistance Calculation - " Proc ISCAS 198o, pp loZo-lo26
• 4: Yoshimura, H., Tansho, K., Ohwada, N., Nishide, T., "An Algorithm for Resistance Calculation from IC Mask Pattern information", Proc. ISCAS 1979, pp. 478-481.
• 5: J. D. Bastian , M. Ellement , P. J. Fowler , C. E. Huang , L. P. McNamee, Symbolic Parasitic Extractor for Circuit Simulation (SPECS), Proceedings of the 20th conference on Design automation, p.346-352, June 27-29, 1983, Miami Beach, Florida, United States
• 6: Horowitz, M., Dutton, R.W., "Resistance Extraction from Mask Layout Data", IEEE Trans. CAD, Vol. 2 (1983), pp. 145-15o.
• 7: Green, H.E., "The Numerical Solution of Some Important Transmission-Line Problems", IEEE Trans. Microwave Theory Tech., Vol. ;3 (1965), pp. 676-692.
• 8: Herskowitz, G.J., "Computer-Aided Integrated Circuit Design", Mc Graw Hill, New York 1968, ch. Io.
• 9: Schneider, M,V., "Computation of Impedance and Attenuation of TEM-Lines by Finite Difference Methods", IEEE Trans. Microwave Theory Tech., Vol. 13 (1965), pp. 793-800.
• 10: Okamura, Y., Muraishi, Y., Sato, T., Ikemoto, Y,, "LAS : Layout Pattern Analysis System with New Approach", Proc. ICCC 1982, pp. 3o8-311.
• 11: Chawla, B.R., Gummel, H.K., "A Boundary Technique for Calculation of Distributed Resistance", IEEE Trans. Electron Devices, Vol 17 (197o), pp. 915-925.
• 12: Sakkas, C.M., "Potential Distribution and Multi-Terminal DC Resistance Computation for LSI Technology~', IBM J. Res. Develop., Vol. 23 (1979), pp. 640-651.
• 13: Mitsuhashi, T., ~amada, H., Yoshida, K., "An LSI Mask Artwork Verification System", Proc. ICCD 1983.
• 14: Berger, H., "Modellbeschrelbung planarer ohmscher Metall-Halbleiterkontakte , PhD Thesis, RWTH Aachen, 197o.
• 15: Murrmann, H., gidmann, D., "Messung des Uebergangswlderstandes zwlschen Me,all und Diffusionsschicht in Si-Planarelementen" Solid State Electronics, Vol. 12 (1969), pp. 879-886.
• 16: Barke, E., "FERKEL : Technologleunabhaengiges direktivengesteuertes Frogrammsystem zur Entwurfsregelnpruefung integrlerter Schaltungen", To be published.

INDEX TERMS

Primary Classification:
  G. Mathematics of Computing
  G.1 NUMERICAL ANALYSIS
      G.1.8 Partial Differential Equations
          Subjects: Finite element methods

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Verification; Layout

  J. Computer Applications

General Terms:
Algorithms, Design, Performance, Theory, Verification