Magic's circuit extractor

ABSTRACT

We have implemented a fast hierarchical circuit extractor for the Magic VLSI layout system. The keys to its speed are a new algorithm based on corner-stitching, and its ability to extract cells incrementally. Because the extractor is incremental, typically only a few cells must be re-extracted when the layout changes. The extractor computes circuit connectivity and transistor dimensions, both internodal and substrate parasitic capacitance, and parasitic resistances. It is parameterized to work across a wide range of MOS technologies.

REFERENCES

• BHE83: J. D. Bastian , M. Ellement , P. J. Fowler , C. E. Huang , L. P. McNamee, Symbolic Parasitic Extractor for Circuit Simulation (SPECS), Proceedings of the 20th conference on Design automation, p.346-352, June 27-29, 1983, Miami Beach, Florida, United States
• Fit82: D.T. Fitzpatrick, "MEXTRA: A Manhattan Circuit Extractor", Electronics Research Lab. Memo M82/42, Electronics Research Laboratory, University of California, Berkeley, January 1982.
• Gup83: Anoop Gupta, ACE: A Circuit Extractor, Proceedings of the 20th conference on Design automation, p.721-725, June 27-29, 1983, Miami Beach, Florida, United States
• McC84: Steven P. McCormick, EXCL: A circuit extractor for IC designs, Proceedings of the 21st conference on Design automation, p.616-623, June 25-27, 1984, Albuquerque, New Mexico, United States
• NeS83: B.J. Nelson and M. A. Shand, "An Integrated, Technology Independent, High Performance Artwork Analyzer for VLSI Circuit Design", Technical Report VLSI-Tech. Rep.-83-4-1, VLSI Program, Division of Computing Research, CSIRO, Eastwood, SA 5063, Australia, April 1983.
• NeF82: M.E. Newell and D. T. Fitzpatrick, "Exploiting Structure in Integrated Circuit Design Analysis", Proceedings of the Conference on Advanced Research in VLSI, MIT, MIT, Boston, Mass., January 1982.
• Ous84: J. Ousterhout, "Corner Stitching: A Data-Structuring Technique for VLSI Layout Tools", IEEE Transactions on CAD/ICAS CAD-3, 1 (January 1984).
• OHM84: John K. Ousterhout , Gordon T. Hamachi , Robert N. Mayo , Walter S. Scott , George S. Taylor, Magic: A VLSI layout system, Proceedings of the 21st conference on Design automation, p.152-159, June 25-27, 1984, Albuquerque, New Mexico, United States
• Ous84: John K. Ousterhout, Switch-level delay models for digital MOS VLSI, Proceedings of the 21st conference on Design automation, p.542-548, June 25-27, 1984, Albuquerque, New Mexico, United States
• Sco84: W.S. Scott, Technology Independent Layout Representation in Magic, Master's Report, University of California, Berkeley, December 1984.
• SpN83: R.L. Spiekelmier and A. R. Newton, "Wombat: A New Netlist Comparison Program", IEEE International Conference on CAD, September 1983, 170-171.
• TaH83: Gary M. Tarolli , William J. Herman, Hierarchical circuit extraction with detailed parasitic capacitance, Proceedings of the 20th conference on Design automation, p.337-345, June 27-29, 1983, Miami Beach, Florida, United States
• UBF84: David Ungar , Ricki Blau , Peter Foley , Dain Samples , David Patterson, Architecture of SOAR: Smalltalk on a RISC, Proceedings of the 11th annual international symposium on Computer architecture, p.188-197, January 1984
• Wag84: Todd J. Wagner, Hierarchical layout verification, Proceedings of the 21st conference on Design automation, p.484-489, June 25-27, 1984, Albuquerque, New Mexico, United States
• Wes81: Neil Weste, Virtual grid symbolic layout, Proceedings of the 18th conference on Design automation, p.225-233, June 29-July 01, 1981, Nashville, Tennessee, United States

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Layout; Simulation
  B.8 Performance and Reliability

  J. Computer Applications

General Terms:
Algorithms, Design, Measurement, Performance, Theory