Design for testability in a silicon compilation environment

ABSTRACT

This paper discusses design for testability automation within a silicon compiler environment under development at GTE Laboratories Inc. The proposed rule-based modular design for testability methodology utilizes both BIST and scan path techniques for full custom VLSI designs. An on-chip test controller may be used. Testability evaluation is performed using both controllability/observability and information theoretic methods. A testability “expert” is required which can manage the analysis as it evolves during the synthesis process and which can make the ultimate testability decisions. Problems involved with integrating the approach with an emerging silicon compilation system are discussed.

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability

Additional Classification:
  B. Hardware
  B.1 CONTROL STRUCTURES AND MICROPROGRAMMING
      B.1.4 Microprogram Design Aids
          Subjects: Languages and compilers
  B.7 INTEGRATED CIRCUITS

  J. Computer Applications

General Terms:
Design, Languages, Performance, Theory