ACTAS: an accurate timing analysis system for VLSI

ABSTRACT

This paper describes a timing analysis system (ACTAS: ACcurate Timing Analysis System). This system analyzes the logical behaviors of VLSI. It verifies timings at flip-flops and detects timing errors. Then, it calculates path delays of the partial combinational circuits generating the errors. If they do not satisfy timing constraints, the system detects error paths. In this system, the former method based on behavior analysis is called DYNAMIC TIMING ANALYSIS and the latter method based on path analysis is called STATIC TIMING ANALYSIS. By use of this system, it improves the timing analysis efficiency of the complicated timing of VLSI.

REFERENCES

• 1: Kazuyuki Hirakawa , Noboru Shiraki , Michiaki Muraoka, Logic simulation for LSI, Proceedings of the 19th conference on Design automation, p.755-761, January 1982
• 2: Thomas M. McWilliams, Verification of timing constraints on large digital systems, Proceedings of the 17th conference on Design automation, p.139-147, June 23-25, 1980, Minneapolis, Minnesota, United States [doi>10.1145/800139.804523]
• 3: Robert B. Hitchcock, Sr., Timing Verification and the Timing Analysis program, Proceedings of the 19th conference on Design automation, p.594-604, January 1982
• 4: Tohru Sasaki , Akihiko Yamada , Toshinori Aoyama , Katsutoshi Hasegawa , Shunichi Kato , Shinichi Sato, Hierarchical design verification for large digital systems, Proceedings of the 18th conference on Design automation, p.105-112, June 29-July 01, 1981, Nashville, Tennessee, United States
• 5: Ryotaro Kamikawai , Minoru Yamada , Tsuneyo Chiba , Kenichi Furumaya , Yoji Tsuchiya, A critical path delay check system, Proceedings of the 18th conference on Design automation, p.118-123, June 29-July 01, 1981, Nashville, Tennessee, United States

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.6 LOGIC DESIGN
      B.6.1 Design Styles
          Subjects: Combinational logic

  J. Computer Applications

General Terms:
Design, Measurement, Performance, Theory