MCNC's vertically integrated symbolic design system

ABSTRACT

This paper describes the VIVID (Vertically Integrated VLSI Design) System developed at the Microelectronics Center of North Carolina. The system is based on a symbolic, virtual-grid design methodology that greatly reduces the design time for custom VLSI circuits. This methodology has made it possible to provide, in a single integrated system, several unique features: technology independent tools for a wide range of MOS processes (CMOS, nMOS, SOI); scale independent circuit designs; open architecture that simplifies both integration with existing tools and creation of new tools; fast layout debugging using symbolic level circuit simulation; and fully automated mask generation and automated chip assembly.

REFERENCES

• EADE76: EADES, J. D. "q'he Design of an Interactive Computer System for Microelectronics Mask Making," PhD Thesis, University of FAinburgh, (1976).
• ENTE85: George Entenman , Stephen W. Daniel, A fully automatic hierarchical compactor, Proceedings of the 22nd ACM/IEEE conference on Design automation, p.69-75, June 1985, Las Vegas, Nevada, United States [doi>10.1145/317825.317835]
• HELL82: William R. Heller , G. Sorkin , Klim Maling, The planar package planner for system designers, Proceedings of the 19th conference on Design automation, p.253-260, January 1982
• HON80: HON, ROBERT W. AND CARLO H SEQUIN, A Guide to LSI Implementation, Xerox PARC, Palo Alto, CA (I98O).
• HSUE79: HSUEH, D. O. AND O. O. PEDERSON, "C~mputer-aided Layout Of LSI Circuit Building-blocks," Proceed~'ngs 197'9 Iscas, pp. 474-477 (1979).
• JOHA79: JOHANNSEN, D, "Bristle Blocks: A Silicon Compiler," in Proceedings of the Cal Tech Conference on VLSI, (January 1979).
• KELL81: KELLER, K. H, "KIC2 A Graphics Editor for Integrated Circuits," Masters Thesis, EECS Dept, U.C. Berkeley, (~981).
• LEE61: LEE, C. Y, "An Algorithm for Path Connections and Its Applications," IRE: Transactions on Electronic Computers EC-10(3) pp. 346-365 (September 1961).
• MUDG80: MUDGE, I. CRAIg, C. PETERS, AND O. M. TAROLLI, "A VLSI Chip Assembler," pp. 329-355 in Design Methodologies for VLSI, NATO Advanced Summer Institute, Belgium (1980).
• NEWE83: NEWELL, SYDNEY B., AART J. DE GEUS, AND RONALD A. RHORER, "'De~dgn Automation for Integrated Circuits," Science 220(4596) pp. 465.-471 (April 29, 1983).
• OUST81: OUSTERHOUT, JOHN K. "Caesar:. An Inte:ractive Editor for VLSI Layouts," VLSI Design, pp. 34-38 (Fourth Quarter, 1981).
• OUST83: John K. Ousterhout , Gordon T. Hamachi , Robert N Mayo , Walter S Scott , George S. Taylor, A Collection of Papers on Magic, University of California at Berkeley, Berkeley, CA, 1983
• Pinter 1981: PINTER, RON Y., "Optimal Routing in Rectilinear Channels (for VLSI)," in Unpublished Research Repot-t, MIT Laboratory for .Computer Science, Cambridge, MA (April 15, 1981).
• ROSE83b: ROSENBERG, JONATHAN B. AND NEIL H. E. WESTE, "ABCD - A Better Circuit Description," MCNC Tech. Rep. No. 4983-O1, Microelectronies Center of NC, RTP, NC 27709 (Feb. 1983).
• ROSE85: ROSENBERG, JONATHAN B., "Geographical Data Structures Compared: A Study of Data Structures Supporting Region Queries," IEEE Trans. on Computer-Aided Design CAD- 4(1XJan. 1985).
• SISK82: SISKIND, JEFFREY M., JAY R. SOUTHARD, AND KENNETH W. CROUCH, "'Generating Custom High Performance VLSI Designs From Succinct Algorithmic Descriptions," MIT Conferer~'e on Advanced Research in VLSI, pp. 28-40 (1982).
• SMIT85: SMITH, PHILIP O. AND STEPHEN W. DANIEL, "The M~ater Technology Fries System for Technology Independence," Proc. 22rid Design Automation ConjL {forthcoming}, (June 1985).
• WATA84: WATANABE, HIRC)YUKI, 1C Layout Generation and Compaction Using Mathematical Ot,timizat~on, Semiconductor Research (~rporation, Research Triangle Park NC (February 1984).
• WEST81a: Neil Weste, Virtual grid symbolic layout, Proceedings of the 18th conference on Design automation, p.225-233, June 29-July 01, 1981, Nashville, Tennessee, United States

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.2 Design Aids
          Subjects: Verification; Layout

General Terms:
Design, Performance, Theory, Verification