An architectural solution for the inductive noise problem due to clock-gating

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An architectural solution for the inductive noise problem due to clock-gating

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1999 international symposium on Low power electronics and design table of contents

San Diego, California, United States

Pages: 255 - 257

Year of Publication: 1999

ISBN:1-58113-133-X

Authors

Mondira Deb Pant	Georgia Institute of Technology, Atlanta, GA
Pankaj Pant
D. Scott Wills	Georgia Institute of Technology, Atlanta, GA
Vivek Tiwari	Intel Corporation, Santa Clara, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 16, Citation Count: 13

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	BAKOGLU, H. B. Circuits, lnterconnections and Packaging for VLSI. Addison-Wesley, 1990.
	2	BURGER, D., AND AUSTIN, T. M. The SimpleScalar tool set, version 2.0. Tech. Rep. 1342, Univ. of Wisconsin-Madison Computer Science Department, June 1997.
	3	Yi-Shing Chang , Sandeep K. Gupta , Melvin A. Breuer, Analysis of Ground Bounce in Deep Sub-Micron Circuits, Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), p.110, April 27-May 01, 1997
	4	Howard W. Johnson , Martin Graham, High-speed digital design: a handbook of black magic, Prentice-Hall, Inc., Upper Saddle River, NJ, 1993
	5	SENTHINATHAN, R., AND PRINCE, J.L. Simultaneous switching ground noise calculation for packaged CMOS devices. IEEE Journal of Solid-State Circuits 26, 11 (Nov 1991), 1724-1728.
	6	Vivek Tiwari , Deo Singh , Suresh Rajgopal , Gaurav Mehta , Rakesh Patel , Franklin Baez, Reducing power in high-performance microprocessors, Proceedings of the 35th annual conference on Design automation, p.732-737, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277227]

CITED BY 13

	Suhwan Kim , Stephen V. Kosonocky , Daniel R. Knebel, Understanding and minimizing ground bounce during mode transition of power gating structures, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Wael El-Essawy , David H. Albonesi , Balaram Sinharoy, A microarchitectural-level step-power analysis tool, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Han-Saem Yun , Jihong Kim, Power-aware modulo scheduling for high-performance VLIW processors, Proceedings of the 2001 international symposium on Low power electronics and design, p.40-45, August 2001, Huntington Beach, California, United States
	Michael D. Powell , T. N. Vijaykumar, Pipeline damping: a microarchitectural technique to reduce inductive noise in supply voltage, ACM SIGARCH Computer Architecture News, v.31 n.2, May 2003
	Vijay Raghunathan , Srivaths Ravi , Anand Raghunathan , Ganesh Lakshminarayana, Transient power management through high level synthesis, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Michael D. Powell , T. N. Vijaykumar, Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Suhwan Kim , Stephen V. Kosonocky , Daniel R. Knebel , Kevin Stawiasz, Experimental measurement of a novel power gating structure with intermediate power saving mode, Proceedings of the 2004 international symposium on Low power electronics and design, August 09-11, 2004, Newport Beach, California, USA
	Weiping Liao , Lei He, Power modeling and reduction of VLIW processors, Compilers and operating systems for low power, Kluwer Academic Publishers, Norwell, MA, 2003
	Michael Healy , Fayez Mohamood , Hsien-Hsin S. Lee , Sung Kyu Lim, A unified methodology for power supply noise reduction in modern microarchitecture design, Proceedings of the 2008 conference on Asia and South Pacific design automation, January 21-24, 2008, Seoul, Korea
	David M. Brooks , Pradip Bose , Stanley E. Schuster , Hans Jacobson , Prabhakar N. Kudva , Alper Buyuktosunoglu , John-David Wellman , Victor Zyuban , Manish Gupta , Peter W. Cook, Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors, IEEE Micro, v.20 n.6, p.26-44, November 2000
	Fayez Mohamood , Michael B. Healy , Sung Kyu Lim , Hsien-Hsin S. Lee, A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design, Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture, p.3-14, December 09-13, 2006
	Shu Xiao , Edmund M.-K. Lai, VLIW instruction scheduling for minimal power variation, ACM Transactions on Architecture and Code Optimization (TACO), v.4 n.3, p.18-es, September 2007
	Hongbo Yang , Guang R. Gao , Clement Leung, On achieving balanced power consumption in software pipelined loops, Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems, October 08-11, 2002, Grenoble, France