Software trace cache

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Software trace cache

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International Conference on Supercomputing archive
Proceedings of the 13th international conference on Supercomputing table of contents

Rhodes, Greece

Pages: 119 - 126

Year of Publication: 1999

ISBN:1-58113-164-X

Authors

Alex Ramírez	Computer Architecture Department, Universitat Politècnica de Catalunya, Jordi Girona 1-3, Module D6, 08034 Barcelona (Spain)
Josep-L. Larriba-Pey	Computer Architecture Department, Universitat Politècnica de Catalunya, Jordi Girona 1-3, Module D6, 08034 Barcelona (Spain)
Carlos Navarro	Computer Architecture Department, Universitat Politècnica de Catalunya, Jordi Girona 1-3, Module D6, 08034 Barcelona (Spain)
Josep Torrellas	University of Illinois at Urbana Champaign and Computer Architecture Department, Universitat Politècnica de Catalunya, Jordi Girona 1-3, Module D6, 08034 Barcelona (Spain)
Mateo Valero	Computer Architecture Department, Universitat Politècnica de Catalunya, Jordi Girona 1-3, Module D6, 08034 Barcelona (Spain)

Sponsor

SIGARCH: ACM Special Interest Group on Computer Architecture

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 18, Citation Count: 17

Additional Information:

references cited by index terms collaborative colleagues peer to peer

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	W. Y. Chen , P. P. Chang , T. M. Conte , W. W. Hwu, The Effect of Code Expanding Optimizations on Instruction Cache Design, IEEE Transactions on Computers, v.42 n.9, p.1045-1057, September 1993 [doi>10.1109/12.241594]
	2	Thomas M. Conte , Kishore N. Menezes , Patrick M. Mills , Burzin A. Patel, Optimization of instruction fetch mechanisms for high issue rates, Proceedings of the 22nd annual international symposium on Computer architecture, p.333-344, June 22-24, 1995, S. Margherita Ligure, Italy
	3	J. A. Fisher. Trace scheduling: A technique for global microcode compaction, iEEE 2~ansactions on Computers, 30(7):478-490, July 1981.
	4	Daniel Holmes Friendly , Sanjay Jeram Patel , Yale N. Patt, Alternative fetch and issue policies for the trace cache fetch mechanism, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.24-33, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	5	Nikolas Gloy , Trevor Blackwell , Michael D. Smith , Brad Calder, Procedure placement using temporal ordering information, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.303-313, December 01-03, 1997, Research Triangle Park, North Carolina, United States
	6	Amir H. Hashemi , David R. Kaeli , Brad Calder, Efficient procedure mapping using cache line coloring, Proceedings of the ACM SIGPLAN 1997 conference on Programming language design and implementation, p.171-182, June 16-18, 1997, Las Vegas, Nevada, United States
	7	W. W. Hwu , P. P. Chang, Achieving high instruction cache performance with an optimizing compiler, Proceedings of the 16th annual international symposium on Computer architecture, p.242-251, April 1989, Jerusalem, Israel
	8	J. Kalamatianos , D. Kaeli, Temporal-Based Procedure Reordering for Improved Instruction Cache Performance, Proceedings of the 4th International Symposium on High-Performance Computer Architecture, p.244, January 31-February 04, 1998
	9	Sanjay Jeram Patel , Marius Evers , Yale N. Patt, Improving trace cache effectiveness with branch promotion and trace packing, Proceedings of the 25th annual international symposium on Computer architecture, p.262-271, June 27-July 02, 1998, Barcelona, Spain
	10	Karl Pettis , Robert C. Hansen, Profile guided code positioning, Proceedings of the ACM SIGPLAN 1990 conference on Programming language design and implementation, p.16-27, June 1990, White Plains, New York, United States
	11	A. Ramlrez, J. L. Laxriba-Pey, C. Navarro, X. Serrano, J. Torrellas, and M. Valero. Code reordering of decision support systems for optimized instruction fetch. Technical Report UPC-DAC-1998-56, Universitat Politecnica de Catalunya, Dec. 1998.
	12	Eric Rotenberg , Steve Bennett , James E. Smith, Trace cache: a low latency approach to high bandwidth instruction fetching, Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture, p.24-35, December 02-04, 1996, Paris, France
	13	J. Torrellas , Chun Xia , R. Daigle, Optimizing instruction cache performance for operating system intensive workloads, Proceedings of the 1st IEEE Symposium on High-Performance Computer Architecture, p.360, January 22-25, 1995
	14	Tse-Yu Yeh , Deborah T. Marr , Yale N. Patt, Increasing the instruction fetch rate via multiple branch prediction and a branch address cache, Proceedings of the 7th international conference on Supercomputing, p.67-76, July 19-23, 1993, Tokyo, Japan [doi>10.1145/165939.165956]

CITED BY 17

	Matthew C. Merten , Andrew R. Trick , Erik M. Nystrom , Ronald D. Barnes , Wen-mei W. Hmu, A hardware mechanism for dynamic extraction and relayout of program hot spots, ACM SIGARCH Computer Architecture News, v.28 n.2, p.59-70, May 2000
	Michael Behar , Avi Mendelson , Avinoam Kolodny, Trace cache sampling filter, ACM Transactions on Computer Systems (TOCS), v.25 n.1, p.3-es, February 2007
	Paramjit S. Oberoi , Gurindar S. Sohi, Parallelism in the front-end, ACM SIGARCH Computer Architecture News, v.31 n.2, May 2003
	Oliverio J. Santana , Alex Ramirez , Josep L. Larriba-Pey , Mateo Valero, A low-complexity fetch architecture for high-performance superscalar processors, ACM Transactions on Architecture and Code Optimization (TACO), v.1 n.2, p.220-245, June 2004
	Ravi Bhargava , Lizy K. John, Latency and energy aware value prediction for high-frequency processors, Proceedings of the 16th international conference on Supercomputing, June 22-26, 2002, New York, New York, USA
	Alex Ramirez , Luiz André Barroso , Kourosh Gharachorloo , Robert Cohn , Josep Larriba-Pey , P. Geoffrey Lowney , Mateo Valero, Code layout optimizations for transaction processing workloads, ACM SIGARCH Computer Architecture News, v.29 n.2, p.155-164, May 2001
	Alex Ramirez , Josep L. Larriba-Pey , Mateo Valero, Software Trace Cache, IEEE Transactions on Computers, v.54 n.1, p.22-35, January 2005
	Xianglong Huang , Stephen M. Blackburn , David Grove , Kathryn S. McKinley, Fast and efficient partial code reordering: taking advantage of dynamic recompilatior, Proceedings of the 2006 international symposium on Memory management, June 10-11, 2006, Ottawa, Ontario, Canada
	Alex Ramirez , Oliverio J. Santana , Josep L. Larriba-Pey , Mateo Valero, Fetching instruction streams, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
	Daniel A. Jiménez, Code placement for improving dynamic branch prediction accuracy, ACM SIGPLAN Notices, v.40 n.6, June 2005
	Alex Ramirez , Josep Ll. Larriba-Pey , Carlos Navarro , Mateo Valero , Josep Torrellas, Software Trace Cache for Commercial Applications, International Journal of Parallel Programming, v.30 n.5, p.373-395, October 2002
	Yoav Almog , Roni Rosner , Naftali Schwartz , Ari Schmorak, Specialized Dynamic Optimizations for High-Performance Energy-Efficient Microarchitecture, Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization, p.137, March 20-24, 2004, Palo Alto, California
	S. Bartolini , C. A. Prete, Optimizing instruction cache performance of embedded systems, ACM Transactions on Embedded Computing Systems (TECS), v.4 n.4, p.934-965, November 2005
	Roni Rosner , Micha Moffie , Yiannakis Sazeides , Ronny Ronen, Selecting long atomic traces for high coverage, Proceedings of the 17th annual international conference on Supercomputing, June 23-26, 2003, San Francisco, CA, USA
	A. Mahjur , A. H. Jahangir , A. H. Gholamipour, On the performance of trace locality of reference, Performance Evaluation, v.60 n.1-4, p.51-72, May 2005
	Michael Dupré , Nathalie Drach , Olivier Temam, VHC: Quickly Building an Optimizer for Complex Embedded Architectures, Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization, p.53, March 20-24, 2004, Palo Alto, California
	Ho-Seop Kim , James E. Smith, Dynamic binary translation for accumulator-oriented architectures, Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization, March 23-26, 2003, San Francisco, California