Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	D. Boyer, "Symbolic compaction benchmarks", Proc. Int. Conf. on Computer Design, pp. 186-191; 209-217, 1987.
	2	Christopher Kingsley, A hiererachical, error-tolerant compactor, Proceedings of the 21st conference on Design automation, p.126-132, June 25-27, 1984, Albuquerque, New Mexico, United States
	3	P. Eichenberger and M. Horowitz, "Toroidal compaction of symbolic layouts for regular structures", Proc. ICCAD, pp. 142-145, 1987.
	4	K. Mehlhom and W. Rulling, "Compaction on the toms", IEEE trans on CAD, vol. 9, No. 4, pp. 389- 397, Apr. 1990.
	5	D. Marple, M. Smulders and H. Hegen, "Tailor: A layout system based on trapezoidal comer stitching", IEEE trans on CAD, vol. 9, No. 1, pp. 66- 90, Jan. 1990.
	6	C. S. Bamji , R. Varadarajan, Hierarchical pitchmatching compaction using minimum design, Proceedings of the 29th ACM/IEEE conference on Design automation, p.311-317, June 08-12, 1992, Anaheim, California, United States
	7	W. Kim , J. Lee , H. Shin, A new hierarchical layout compactor using simplified graph models, Proceedings of the 29th ACM/IEEE conference on Design automation, p.323-326, June 08-12, 1992, Anaheim, California, United States
	8	H. Shin, A. L. Sangiovanni-Vincentelli, and C. H. Sequin, "Two-dimensional module compactor based on zonerefining", Proc. Int. Conf. on Computer Design, pp. 201-203, 1987.
	9	Chi-Yuan Lo , Ravi Varadarajan, An O(n1.5logn) 1-d compaction algorithm, Proceedings of the 27th ACM/IEEE conference on Design automation, p.382-387, June 24-27, 1990, Orlando, Florida, United States  [doi>10.1145/123186.123312]
	10	David Marple, A hierarchy preserving hierarchical compactor, Proceedings of the 27th ACM/IEEE conference on Design automation, p.375-381, June 24-27, 1990, Orlando, Florida, United States  [doi>10.1145/123186.123311]
	11	Cyrus S. Bamji , Charles E. Hauck , Jonathan Allen, A design by example regular structure generator, Proceedings of the 22nd ACM/IEEE conference on Design automation, p.16-22, June 1985, Las Vegas, Nevada, United States  [doi>10.1145/317825.317828]
	12	M. Y. Hsueh, "Symbolic layout and compaction of integrated circuits", ERL Memo, UCB/ERL M79/80, Univ. of Berkeley, Dec. 1979.
	13	J. F. Lee, "A new framework of design rules for compaction of VLSI layouts", IEEE trans on CAD, vol. 7, No. 11, pp. 1195- 1204, Nov 1988.
	14	Optimization Subroutine Library, IBM manual SC23-0519-02

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