Verifying clock schedules

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Verifying clock schedules

Full text

Pdf (872 KB)

Source

International Conference on Computer Aided Design archive
Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design table of contents

Santa Clara, California, United States

Pages: 124 - 131

Year of Publication: 1992

ISBN:0-89791-540-2

Authors

Thomas G. Szymanski	AT&T Bell Laboratories, Murray Hill, NJ
Narendra Shenoy	University of California, Berkeley, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 13, Citation Count: 19

Additional Information:

references cited by index terms collaborative colleagues peer to peer

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	BSM92	Timothy M. Burks, Karem A. Saka/lah, and Trevor N. Mudge. Multi-phase retiming using min Te. In A GM/SIGDA Workshop on Timing lssues in the Specification and Synthesis of Digital Systems, March 1992.
	IL90	Alexander T. Ishii , Charles E. Leiserson, A timing analysis of level-clocked circuitry, Proceedings of the sixth MIT conference on Advanced research in VLSI, p.113-130, March 1990, Boston, Massachusetts, United States
	LB92	Wei-Han Lien and Wayne Burleson. Wavedomino logic: Timing analysis and applications. In A CM/SIGDA Workshop on Timing Issues in the Specification and Synthesis o/ Digital Systems, March 1992.
	SBSV92	Narendra Shenoy, Robert K. Brayton, and Alberto L. Sangiovanni-Vincentelli. A pseudopolynomial algorithm for verification of clocking schemes. In A CM/SIGDA Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, March 1992.
	SMO90	Karem A. Sakallah, Trevor N. Mudge, and Oyekunle A. Olukotun. check Tc and rain T~ : timing verification and optimal clocking of synchronous digital circuits. In Digest of Technical Papers of the 1EEE International Conference on Computer-Aided Design, pages 552- 555, November 1990.
	SMO92	Karem A. Sakallah, Trevor N. Mudge, and Oyekunle A. Olukotun. Analysis and design of latch-controlled synchronous digital circuits. 1EEE Transactions on Computer-Aided Design of Integrated Circuits, 11(3):322-333, March 1992.
	Szy92	T. G. Szymanski, Computing optimal clock schedules, Proceedings of the 29th ACM/IEEE conference on Design automation, p.399-404, June 08-12, 1992, Anaheim, California, United States
	TL91	Ren-Song Tsay and Ichiang Lin. A system timing verifier for multi-phase level-sensitive clock designs. Technical Report RC 17272, IBM, October 1991.

CITED BY 19

	Jin-fuw Lee , Donald T. Tang, An algorithm for incremental timing analysis, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.696-701, June 12-16, 1995, San Francisco, California, United States
	Jin-fuw Lee , Donald T. Tang , C. K. Wong, A timing analysis algorithm for circuits with level-sensitive latches, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.743-748, November 06-10, 1994, San Jose, California, United States
	Timothy M. Burks , Karem A. Sakallah , Trevor N. Mudge, Identification of critical paths in circuits with level-sensitive latches, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.137-141, November 1992, Santa Clara, California, United States
	P. Vuillod , L. Benini , A. Bogliolo , G. De Micheli, Clock skew optimization for peak current reduction, Proceedings of the 1996 international symposium on Low power electronics and design, p.265-270, August 12-14, 1996, Monterey, California, United States
	Masamichi Kawarabayashi , Narendra Shenoy , Alberto Sangiovanni-Vincentelli, A verification technique for gated clock, Proceedings of the 30th international conference on Design automation, p.123-127, June 14-18, 1993, Dallas, Texas, United States
	Ruiming Chen , Hai Zhou, Clock schedule verification under process variations, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.619-625, November 07-11, 2004
	Hai Zhou, Clock schedule verification with crosstalk, Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems, December 02-03, 2002, Monterey, California, USA
	Hai Zhou, Timing Verification with Crosstalk for Transparently Latched Circuits, Proceedings of the conference on Design, Automation and Test in Europe, p.10056, March 03-07, 2003
	Baris Taskin , Ivan S. Kourtev, Performance optimization of single-phase level-sensitive circuits using time borrowing and non-zero clock skew, Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems, December 02-03, 2002, Monterey, California, USA
	C. Albrecht , B. Korte , J. Schietke , J. Vygen, Cycle time and slack optimization for VLSI-chips, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.232-238, November 07-11, 1999, San Jose, California, United States
	Christoph Albrecht , Bernhard Korte , Jürgen Schietke , Jens Vygen, Maximum mean weight cycle in a digraph and minimizing cycle time of a logic chip, Discrete Applied Mathematics, v.123 n.1-3, p.103-127, 15 November 2002
	Soha Hassoun, Critical path analysis using a dynamically bounded delay model, Proceedings of the 37th conference on Design automation, p.260-265, June 05-09, 2000, Los Angeles, California, United States
	Chuan Lin , Hai Zhou, Trade-off between latch and flop for min-period sequential circuit designs with crosstalk, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.329-334, November 06-10, 2005, San Jose, CA
	Marios C. Papaefthymiou , Keith H. Randall, TIM: a timing package for two-phase, level-clocked circuitry, Proceedings of the 30th international conference on Design automation, p.497-502, June 14-18, 1993, Dallas, Texas, United States
	Yuji Kukimoto , Michel Berkelaar , Karem Sakallah, Static timing analysis, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Alexander T. Ishii , Charles E. Leiserson , Marios C. Papaefthymiou, Optimizing two-phase, level-clocked circuitry, Journal of the ACM (JACM), v.44 n.1, p.148-199, Jan. 1997
	Yuegang Tao , Guo-Ping Liu , Wende Chen, Globally optimal solutions of max---min systems, Journal of Global Optimization, v.39 n.3, p.347-363, November 2007
	Jeremy Gunawardena, From max-plus algebra to nonexpansive mappings: a nonlinear theory for discrete event systems, Theoretical Computer Science, v.293 n.1, p.141-167, 3 February 2003
	Dian Zhou , Rui-Ming Li, Design and verification of high-speed VLSI physical design, Journal of Computer Science and Technology, v.20 n.2, p.147-165, March 2005