An algorithm to reduce test application time in full scan designs

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An algorithm to reduce test application time in full scan designs

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International Conference on Computer Aided Design archive
Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design table of contents

Santa Clara, California, United States

Pages: 17 - 20

Year of Publication: 1992

ISBN:0-89791-540-2

Authors

Soo Y. Lee	Department of Electrical and Computer Engineering, University of Wisconsin - Madison, Madison, WI
Kewal K. Saluja	Department of Electrical and Computer Engineering, University of Wisconsin - Madison, Madison, WI

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 7, Citation Count: 9

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references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	R. Gupta and M. A. Breuer, "Ordering storage elements in a single scan chain," Proc. Intl. Conf. on Computer-Aided Design, pp. 408-411, 1991.
	2	Sean P. Morley , Ralph Marlett, Selectable Length Partial Scan: A Method to Reduce Vector Length, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.385-392, October 26-30, 1991
	3	T. M. Niermann, R. K. Roy, J. H. Patel, and J. A. Abraham, "Test compaction for sequential circuits," IEEE Trans. on Computer-Aided Designs vol. 11, no. 2, pp. 260-267, February 1992.
	4	A. A. Diwan, "An algorithm for minimizing the number of test cycles," Proc. 4th intl. Syrup. on VL$I Design, pp. 154-156, January 1991.
	5	P. Goel and B. C. Rosales, "Test generation & dynamic compaction of tests," Proc. Int. Test Conf., pp. 189-192, 1979.
	6	M. Abramovici, J. J. Kulikowski, P. R. Menon, and D. T. Miller, "SMART and FAST: Test generation for VLSI scan design circuits," IEEE Design and Test of Comp., pp. 43-54, August 1986.
	7	Irith Pomeranz , Lakshmi N. Reddy , Sudhakar M. Reddy, COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.194-203, October 26-30, 1991
	8	D. K. Pradhan and J. Saxena, "A design for testability scheme to reduce test application time," Proceedings VLSI Test Conference, pp. 55-60, April 1992.
	9	F. Brglez, D, Bryan, and K. Kozminski, "Combinational profiles of sequential benchmark circuits," Proc. Intl. Symp. on Circuits and Systems, pp. 1929-1934, May 1989.
	10	T. P. Kelsey , K. K. Saluja , S. Y. Lee, An Efficient Algorithm for Sequential Circuit Test Generation, IEEE Transactions on Computers, v.42 n.11, p.1361-1371, November 1993 [doi>10.1109/12.247839]
	11	Lawrence H. Goldstein , Evelyn L. Thigpen, SCOAP: Sandia controllability/observability analysis program, Proceedings of the 17th conference on Design automation, p.190-196, June 23-25, 1980, Minneapolis, Minnesota, United States [doi>10.1145/800139.804528]

CITED BY 9

	Irith Pomeranz , Sudhakar Reddy, An approach to test compaction for scan circuits that enhances at-speed testing, Proceedings of the 38th conference on Design automation, p.156-161, June 2001, Las Vegas, Nevada, United States
	Irith Pomeranz , Sudhakar M. Reddy, On undetectable faults in partial scan circuits, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.82-86, November 10-14, 2002, San Jose, California
	Irith Pomeranz , Sudhakar M. Reddy, Static Test Compaction for Scan-Based Designs to Reduce Test Application Time, Journal of Electronic Testing: Theory and Applications, v.16 n.5, p.541-552, Oct 2000
	Irith Pomeranz , Sudhakar M. Reddy, Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.7, p.780-788, July 2004
	Irith Pomeranz , Sudhakar M. Reddy, Functional test generation for full scan circuits, Proceedings of the conference on Design, automation and test in Europe, p.396-403, March 27-30, 2000, Paris, France
	Irith Pomeranz , Sudhakar M. Reddy, A New Approach to Test Generation and Test Compaction for Scan Circuits, Proceedings of the conference on Design, Automation and Test in Europe, p.11000, March 03-07, 2003
	Seiji Kajihara , Kohei Miyase, On identifying don't care inputs of test patterns for combinational circuits, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Paul Thadikaran , Sreejit Chakravarty , Janak Patel, Algorithms to compute bridging fault coverage of IDDQ test sets, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.2 n.3, p.281-305, July 1997
	Irith Pomeranz , Sudhakar M. Reddy, On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits, IEEE Transactions on Computers, v.49 n.2, p.175-182, February 2000