Configuring multiple scan chains for minimum test time

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Configuring multiple scan chains for minimum test time

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International Conference on Computer Aided Design archive
Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design table of contents

Santa Clara, California, United States

Pages: 4 - 8

Year of Publication: 1992

ISBN:0-89791-540-2

Authors

Sridhar Narayanan	Dept. of Electrical Engg.-Systems, University of Southern California, Los Angeles, CA
Rajesh Gupta	IBM East Fishkill, Zip 3A1/306, Route 52, Hopewell Jct., NY
Melvin Breuer	Dept. of Electrical Engg.-Systems, University of Southern California, Los Angeles, CA

Sponsors

IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society

Publisher

IEEE Computer Society Press Los Alamitos, CA, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 12, Citation Count: 4

Additional Information:

references cited by index terms collaborative colleagues peer to peer

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	K.-T. Cheng , V. D. Agrawal, A Partial Scan Method for Sequential Circuits with Feedback, IEEE Transactions on Computers, v.39 n.4, p.544-548, April 1990 [doi>10.1109/12.54847]
	2	R. Gupta , M. A. Breuer, The Ballast Methodology for Structured Partial Scan Design, IEEE Transactions on Computers, v.39 n.4, p.538-544, April 1990 [doi>10.1109/12.54846]
	3	P.P. Fasang et al. Automated design for testability of semicustom integrated circuits. In Proc., lnt'l Test Conf., pages 558-564, November 1985.
	4	Sudipta Bhawmik , P. Palchaudhuri, DFT Expert: Designing Testable VLSI Circuits, IEEE Design & Test, v.6 n.5, p.8-19, September 1989 [doi>10.1109/54.43075]
	5	Sean P. Morley , Ralph Marlett, Selectable Length Partial Scan: A Method to Reduce Vector Length, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.385-392, October 26-30, 1991
	6	R.Gupta. Advanced Serial Scan Design for Testability. Ph.D. thesis, Univ. of Southern California, Dept. of Electrical Engg., 1991. CEng. Technical Report 91-10.
	7	M. Abramovici, M. A. Breuer, and A. D. Friedman. Digital Systems Testing and Testable Design. Compurer Science Press, New York, N.Y., 1990.
	8	S. Narayanan , R. Gupta , M. A. Breuer, Optimal Configuring of Multiple Scan Chains, IEEE Transactions on Computers, v.42 n.9, p.1121-1131, September 1993 [doi>10.1109/12.241600]
	9	Thomas T. Cormen , Charles E. Leiserson , Ronald L. Rivest, Introduction to algorithms, MIT Press, Cambridge, MA, 1990

CITED BY 4

	Yoshinobu Higami , Kozo Kinoshita, Design of Partially Parallel Scan Chain, Proceedings of the 1997 European conference on Design and Test, p.626, March 17-20, 1997
	Srimat T. Chakradhar , Anand Raghunathan, Bottleneck removal algorithm for dynamic compaction and test cycles reduction, Proceedings of the conference on European design automation, p.98-104, September 18-22, 1995, Brighton, England
	Chauchin Su, A linear optimal test generation algorithm for interconnect testing, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.290-295, November 08-12, 1998, San Jose, California, United States
	Irith Pomeranz , Sudhakar M. Reddy, Static Test Compaction for Scan-Based Designs to Reduce Test Application Time, Journal of Electronic Testing: Theory and Applications, v.16 n.5, p.541-552, Oct 2000