| Fast temporary storage for serial and parallel execution |
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International Symposium on Computer Architecture
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Proceedings of the 14th annual international symposium on Computer architecture
table of contents
Pittsburgh, Pennsylvania, United States
Pages: 35 - 43
Year of Publication: 1987
ISBN:0-8186-0776-9
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Authors
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J. Swensen
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University of California, Berkeley, CA
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Y. Patt
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University of California, Berkeley, CA
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| Bibliometrics |
Downloads (6 Weeks): 2, Downloads (12 Months): 10, Citation Count: 1
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ABSTRACT
There is an apparent conflict between the hardware requirements for fast parallel execution and the hardware requirements for fast serial execution. For example, fast vector execution is achieved by maintaining high execution concurrency over extended periods of time. With many operations executing in parallel, the time to carry out individual operations is much less important than the average execution concurrency.Fast serial execution, on the other hand, requires rapid execution of relatively few operations at a time; hardware concurrency can be sacrificed in favor of short execution times. Fewer registers and memory locations are required, but they must have shorter access times than for parallel execution.We show how to integrate these seemingly conflicting requirements into a single computer, using asymmetric distribution of hardware, and sometimes using software to allocate variables to appropriate parts of the storage hierarchy.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Cray Research, Inc. 1081. Cray-1 Computer Systems Cray-1 S Hardware Reference Manual, HR-0808. Mendota Heights, Minn.
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Digital Equipment Corporation. VAX-11/780 Central Processor Technical Description, EK-KA780- TD-001, Maynard, Mass.
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Dongarra, Jack J. and Alan Hinds, Comparison of the Cray X-MP-4, Fujitsu VP-eO0, and Hitachi S-810/20: An Argonne Perspective. ANL 85-19, Argonne National Laboratory, 1985.
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Fairchild, ECL Data Book, Fairchild Camera and Instrument Corporation, Mountain View, California, 1977.
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Huffman, D., A Method for the Construction of Minimum-Redundancy Codes Proc. IRE. vol. 40, no. 9, (1952) pp. 1098-1101.
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McMahon, F. H. L.L.N.L. FORTRAN KERNELS: MFLOPS, Lawrence Livermore National Laboratories, 1984.
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Motorola, MECL High Speed Integrated Circuits, Motorola Semiconductor Products, Phoenix, Arizona, 1978.
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CITED BY
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A. Despain , Y. Patt , V. Srini , P. Bitar , W. Bush , C. Chien , W. Citrin , B. Fagin , W. Hwu , S. Melvin , R. McGeer , A. Singhal , M. Shebanow , P. Van Roy, Aquarius, ACM SIGARCH Computer Architecture News, v.15 n.1, p.22-34, March 1987
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