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ABSTRACT
Out-of-order execution and branch prediction are two mechanisms that can be used profitably in the design of Supercomputers to increase performance. Unfortunately this means there must be some kind of repair mechanism, since situations do occur that require the computing engine to repair to a known previous state. One way to handle this is by checkpoint repair. In this paper we derive several properties of checkpoint repair mechanisms. In addition, we provide algorithms for performing checkpoint repair that incur very little overhead in time and modest cost in hardware. We also note that our algorithms require no additional complexity or time for use with write back cache memory systems than they do with write through cache memory systems, contrary to statements made by previous researchers.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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[doi> 10.1145/567532.567555]
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CITED BY 34
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Eric Hao , Po-Yung Chang , Yale N. Patt, The effect of speculatively updating branch history on branch prediction accuracy, revisited, Proceedings of the 27th annual international symposium on Microarchitecture, p.228-232, November 30-December 02, 1994, San Jose, California, United States
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Mayan Moudgill , Keshav Pingali , Stamatis Vassiliadis, Register renaming and dynamic speculation: an alternative approach, Proceedings of the 26th annual international symposium on Microarchitecture, p.202-213, December 01-03, 1993, Austin, Texas, United States
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James E. Wilson , Steve Melvin , Michael Shebanow , Wen-mei Hwu , Yale N. Patt, On tuning the microarchitecture of an HPS implementation of the VAX, Proceedings of the 20th annual workshop on Microprogramming, p.162-167, December 01-04, 1987, Colorado Springs, Colorado, United States
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Stéphan Jourdan , Pascal Sainrat , Daniel Litaize, An investigation of the performance of various instruction-issue buffer topologies, Proceedings of the 28th annual international symposium on Microarchitecture, p.279-284, November 29-December 01, 1995, Ann Arbor, Michigan, United States
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Daniel Holmes Friendly , Sanjay Jeram Patel , Yale N. Patt, Alternative fetch and issue policies for the trace cache fetch mechanism, Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture, p.24-33, December 01-03, 1997, Research Triangle Park, North Carolina, United States
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José F. Martínez , Jose Renau , Michael C. Huang , Milos Prvulovic , Josep Torrellas, Cherry: checkpointed early resource recycling in out-of-order microprocessors, Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture, November 18-22, 2002, Istanbul, Turkey
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Ronald D. Barnes , Erik M. Nystrom , John W. Sias , Sanjay J. Patel , Nacho Navarro , Wen-mei W. Hwu, Beating in-order stalls with "flea-flicker" two-pass pipelining, Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture, p.387, December 03-05, 2003
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Masaitsu Nakajima , Hiraku Nakano , Yasuhiro Nakakura , Tadahiro Yoshida , Yoshiyuki Goi , Yuji Nakai , Reiji Segawa , Takeshi Kishida , Hiroshi Kadota, OHMEGA: a VLSI superscalar processor architecture for numerical applications, ACM SIGARCH Computer Architecture News, v.19 n.3, p.160-168, May 1991
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A. Despain , Y. Patt , V. Srini , P. Bitar , W. Bush , C. Chien , W. Citrin , B. Fagin , W. Hwu , S. Melvin , R. McGeer , A. Singhal , M. Shebanow , P. Van Roy, Aquarius, ACM SIGARCH Computer Architecture News, v.15 n.1, p.22-34, March 1987
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