ACM Home Page
Please provide us with feedback. Feedback
Checkpoint repair for out-of-order execution machines
Full text PdfPdf (841 KB)
Source International Symposium on Computer Architecture archive
Proceedings of the 14th annual international symposium on Computer architecture table of contents
Pittsburgh, Pennsylvania, United States
Pages: 18 - 26  
Year of Publication: 1987
ISBN:0-8186-0776-9
Authors
W. W. Hwu  Computer Science Division, University of California, Berkeley, CA
Y. N. Patt  Computer Science Division, University of California, Berkeley, CA
Sponsor
SIGARCH: ACM Special Interest Group on Computer Architecture
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 12,   Downloads (12 Months): 87,   Citation Count: 34
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues   peer to peer  

Tools and Actions: Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/30350.30353
What is a DOI?

ABSTRACT

Out-of-order execution and branch prediction are two mechanisms that can be used profitably in the design of Supercomputers to increase performance. Unfortunately this means there must be some kind of repair mechanism, since situations do occur that require the computing engine to repair to a known previous state. One way to handle this is by checkpoint repair. In this paper we derive several properties of checkpoint repair mechanisms. In addition, we provide algorithms for performing checkpoint repair that incur very little overhead in time and modest cost in hardware. We also note that our algorithms require no additional complexity or time for use with write back cache memory systems than they do with write through cache memory systems, contrary to statements made by previous researchers.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

1
2
 
3
J. K. L. Lee and A. J. Smith, "Branch Prediction Strategies and Branch Target Buffer Design," IEEE Computer, vol. 17, no. 1, Jan. 1984.
4
5
 
6
D.W. Anderson, F. J. Sparacio, F. J. Tomasulo, "The IBM System/360 Model 91: Machine Philosophy and Instruction Handling", IBM Journal of Research and Development, vol. 11, No.1, pp. 8-24, 1967.
 
7
R.M. Tomasulo, "An Efficient Algorithm for Exploiting Multiple Arithmetic Units," IBM Journal of Research and Development, vol.11, no. 1, pp.25-33, Jan. 1967.
 
8
 
9
S. Weiss and J. E. Smith, "Instruction Issue Logic in Pipelined Supercomputers," IEEE Trans. on Computers, pp. 1013-1022. vol. c-33, No. 11, Nov. 1984.
 
10
DEC, VAX Architeeture Handbook, 1981.
11
 
12
A. J. Smith, "Cache Memories," Computing Surveys, vol.14, No. 8, pp. 478-580, September 1986.
13
 
14
W. W. Hwu and Y. N. Patt, "Design Choices for the HPSm Microprocessor Chip," Proeeedings of the 20th Annual HICSS, pp. 329-336, Jan. 1987.
 
15
W. W. Hwu and Y. N. Patt, "Checkpoint Repair for High Performance Out-of-order Execution Machines," internal report.

CITED BY  34
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 


Peer to Peer - Readers of this Article have also read: