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Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model
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Source International Symposium on Physical Design archive
Proceedings of the 1999 international symposium on Physical design table of contents
Monterey, California, United States
Pages: 133 - 138  
Year of Publication: 1999
ISBN:1-58113-089-9
Authors
Jiang Hu  Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN
Sachin S. Sapatnekar  Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN
Sponsor
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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Downloads (6 Weeks): 2,   Downloads (12 Months): 6,   Citation Count: 3
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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
W. C. Elmore, "The transient response of damped linear network with particular regard to wideband amplitiers," Journal of Applied Physics, Vol. 19, pp. 55-63, 1948.
 
2
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L. T. Pillage and R. A. Rohrer, "Asymptotic waveform evaluation for timing analysis," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Bysterns, Vol. 9, No. 4, pp. 352-366, Apr. 1990.
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J. Qian, S. Pullela and L. T. Pillage, "Modeling the effective capacitance for the RC interconnect of CMOS gates," IF, BE Transactions on Computer.Aided Design of Integrated Circuits and Systems, Vol. 13, No. 12, pp. 1526-35, Dec. 1994.
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K.D. Boese, A. B. Kahng, B. A. McCoy and G. Robins, "Near-optimal critical sink routing tree constructions," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 14, No. 12, pp. 1417- 36, Dec. 1995.
 
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F. J. Liu, J. LiUis and C. K. Cheng, "Design and implementation of a global router based on a new layoutdriven timing model with three poles," Proceedings of the IEEE International Symposium on Circuits and Systems, 1997.
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14
H. Hou, J. Hu and S. S. Sapatnekar, "NonHanan routing", to be published on IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
 
15
L. P. V. Ginneken, "Buffer placement in distributed RC-tree networks for minimal Elmore delay", Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 865-868, 1990.
 
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Y. Jiang, S. S. Sapatnekar, C. Bamji and J. Kim, "Combined transistor sizing with buffer insertion for timing optimization", Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 605-608, 1998.


Collaborative Colleagues:
Jiang Hu: colleagues
Sachin S. Sapatnekar: colleagues