Slicing floorplans with range constraint

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Slicing floorplans with range constraint

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International Symposium on Physical Design archive
Proceedings of the 1999 international symposium on Physical design table of contents

Monterey, California, United States

Pages: 97 - 102

Year of Publication: 1999

ISBN:1-58113-089-9

Authors

F. Y. Young	Department of Computer Sciences, The University of Texas at Austin
D. F. Wong	Department of Computer Sciences, The University of Texas at Austin

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 5, Downloads (12 Months): 15, Citation Count: 7

Additional Information:

references cited by index terms collaborative colleagues peer to peer

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	K. Bazargan , S. Kim , M. Sarrafzadeh, Nostradamus: a floorplanner of uncertain design, Proceedings of the 1998 international symposium on Physical design, p.18-23, April 06-08, 1998, Monterey, California, United States [doi>10.1145/274535.274538]
	2	D.P. Lapotin and S.W. Director. Mason: A global floorplanning tool. Proceedings IEEE International Conference on Computer-Aided Design, pages 143-145, 1985.
	3	H. Murata , K. Fujiyoshi , M. Kaneko, VLSI/PCB placement with obstacles based on sequence-pair, Proceedings of the 1997 international symposium on Physical design, p.26-31, April 14-16, 1997, Napa Valley, California, United States [doi>10.1145/267665.267675]
	4	Hiroshi Murata , Kunihiro Fujiyoshi , Shigetoshi Nakatake , Yoji Kajitani, Rectangle-packing-based module placement, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.472-479, November 05-09, 1995, San Jose, California, United States
	5	Hiroshi Murata , Ernest S. Kuh, Sequence-pair based placement method for hard/soft/pre-placed modules, Proceedings of the 1998 international symposium on Physical design, p.167-172, April 06-08, 1998, Monterey, California, United States [doi>10.1145/274535.274560]
	6	Shigetoshi Nakatake , Kunihiro Fujiyoshi , Hiroshi Murata , Yoji Kajitani, Module placement on BSG-structure and IC layout applications, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.484-491, November 10-14, 1996, San Jose, California, United States
	7	Ralph H.J.M. Otten, Automatic floorplan design, Proceedings of the 19th conference on Design automation, p.261-267, January 1982
	8	R.H.J.M. Otten. Efficient floorplau optimization. IEEB International Conference on Computer Design, pages 499-502, 1983.
	9	Larry Stockmeyer, Optimal orientations of cells in slicing floorplan designs, Information and Control, v.57 n.2-3, p.91-101, May/June 1983 [doi>10.1016/S0019-9958(83)80038-2]
	10	Takayuki Yamanouchi , Kazuo Tamakashi , Takashi Kambe, Hybrid floorplanning based on partial clustering and module restructuring, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.478-483, November 10-14, 1996, San Jose, California, United States
	11	D. F. Wong , C. L. Liu, A new algorithm for floorplan design, Proceedings of the 23rd ACM/IEEE conference on Design automation, p.101-107, July 1986, Las Vegas, Nevada, United States
	12	F. Y. Young , D. F. Wong, How good are slicing floorplans?, Integration, the VLSI Journal, v.23 n.1, p.61-73, Oct. 1997 [doi>10.1016/S0167-9260(97)00014-X]
	13	F. Y. Young , D. F. Wong, Slicing floorplans with pre-placed modules, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.252-258, November 08-12, 1998, San Jose, California, United States [doi>10.1145/288548.288622]
	14	F.Y. Young and D.F. Wong. Slicing floorplans with boundary constraints. IEEE Asia South Pacific Design Automation Conference, pages 17-20, 1999.

CITED BY 7

	Evangeline F. Y. Young , M. L. Ho , Chris C. N. Chu, A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design, Proceedings of the 2002 conference on Asia South Pacific design automation/VLSI Design, p.661, January 07-11, 2002
	En-Cheng Liu , Ming-Shiun Lin , Jianbang Lai , Ting-Chi Wang, Slicing floorplan design with boundary-constrained modules, Proceedings of the 2001 international symposium on Physical design, p.124-129, April 01-04, 2001, Sonoma, California, United States
	I-Min Liu , Hung-Ming Chen , Tan-Li Chou , Adnan Aziz , D. F. Wong, Integrated power supply planning and floorplanning, Proceedings of the 2001 conference on Asia South Pacific design automation, p.589-594, January 2001, Yokohama, Japan
	Wing Seung Yuen , Fung Yu Young, Slicing floorplan with clustering constraints, Proceedings of the 2001 conference on Asia South Pacific design automation, p.503-508, January 2001, Yokohama, Japan
	Evangeline F. Y. Young , Chris C. N. Chu , M. L. Ho, Placement constraints in floorplan design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.7, p.735-745, July 2004
	Jill H. Y. Law , Evangeline F. Y. Young, Multi-bend bus driven floorplanning, Integration, the VLSI Journal, v.41 n.2, p.306-316, February, 2008
	Jianbang Lai , Ming-Shiun Lin , Ting-Chi Wang , Li-C. Wang, Module placement with boundary constraints using the sequence-pair representation, Proceedings of the 2001 conference on Asia South Pacific design automation, p.515-520, January 2001, Yokohama, Japan