Optimal partitioners and end-case placers for standard-cell layout

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Optimal partitioners and end-case placers for standard-cell layout

Full text

Pdf (1.04 MB)

Source

International Symposium on Physical Design archive
Proceedings of the 1999 international symposium on Physical design table of contents

Monterey, California, United States

Pages: 90 - 96

Year of Publication: 1999

ISBN:1-58113-089-9

Authors

A. E. Caldwell	UCLA Computer Science Dept., Los Angeles, CA
A. B. Kahng	UCLA Computer Science Dept., Los Angeles, CA
I. L. Markov	UCLA Computer Science Dept., Los Angeles, CA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 15, Citation Count: 10

Additional Information:

references cited by index terms collaborative colleagues peer to peer

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/299996.300032 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	C. J. Alpert, "Partitioning Benchmarks for VLS! CAD Cnmmunity", Web page, http://vlsicad.cs.ucla.eduFcheese/benchmarks.html (see also the parent home page for partitioning codes).
	2	C. J. Alpert , T. Chan , D. J.-H. Huang , I. Markov , K. Yan, Quadratic placement revisited, Proceedings of the 34th annual conference on Design automation, p.752-757, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266362]
	3	Charles J. Alpert , Jen-Hsin Huang , Andrew B. Kahng, Multilevel circuit partitioning, Proceedings of the 34th annual conference on Design automation, p.530-533, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266275]
	4	Charles J. Alpert , Andrew B. Kahng, Recent directions in netlist partitioning: a survey, Integration, the VLSI Journal, v.19 n.1-2, p.1-81, Aug. 1995 [doi>10.1016/0167-9260(95)00008-4]
	5	J. Clausen and J. L. Trfiff, "Do Inherently Sequential Branchand-Bound Algorithms Exist?", Parallel Processing Letters 4(1-2) (1994). pp. 3-13.
	6	J. A. Davis, V. K. De and J. D. Meindl, "A Stochastic W'ure-Length Distribution for Gigascale Integration (GSI)- Part I: Derivation and Validation", IEEE Transactions on Electron Devices, 45(3) (1998), pp. 580-589.
	7	A. E. Dunlop and B. W. Kernighan, "'A Procedure for Placement of Standard Cell VLSI Circuits", IEEE Transactions on Computer- Aided Design 4(l) ( 1985), pp. 92-98
	8	Shantanu Dutt , Wenyong Deng, VLSI circuit partitioning by cluster-removal using iterative improvement techniques, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.194-200, November 10-14, 1996, San Jose, California, United States
	9	Shantanu Dutt , Halim Theny, Partitioning around roadblocks: tackling constraints with intermediate relaxations, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.350-355, November 09-13, 1997, San Jose, California, United States
	10	C. M. Fiduccia , R. M. Mattheyses, A linear-time heuristic for improving network partitions, Proceedings of the 19th conference on Design automation, p.175-181, January 1982
	11	Lars W. Hagen , Dennis J. H. Huang , Andrew B. Kahng, Quantified suboptimality of VLSI layout heuristics, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.216-221, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217532]
	12	George Karypis , Rajat Aggarwal , Vipin Kumar , Shashi Shekhar, Multilevel hypergraph partitioning: application in VLSI domain, Proceedings of the 34th annual conference on Design automation, p.526-529, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266273]
	13	B. W. Kernighan and S. Lin, "An Efficient Heuristic Proce, dure for Partitioning Graphs" Bell System Tec. Journal 49 (1970) pp. 291- 307.
	14	Jo Kleinhan~. G; Sig\|, E Joh~ne.s_ and K. An_m~_ich0 "GORDIAN: VLSI Placement by Quadratic Programming and Slicing Optimization", IEEE Trans. on Computer Aided Design 10(3) (1991), pp. 356- .7U.1.
	15	Ralph H. J. M. Otten, Global wires: harmful?, Proceedings of the 1998 international symposium on Physical design, p.104-109, April 06-08, 1998, Monterey, California, United States [doi>10.1145/274535.274550]
	16	Ralph H. J. M. Otten , Robert K. Brayton, Planning for performance, Proceedings of the 35th annual conference on Design automation, p.122-127, June 15-19, 1998, San Francisco, California, United States [doi>10.1145/277044.277071]
	17	R. Preis and R. Diekmann, The PARTY Partitioning-Library User Guide, Version 1.1, University of Paded~m, September 1996.
	18	Horst D. Simon , Shang-Hua Teng, How Good is Recursive Bisection?, SIAM Journal on Scientific Computing, v.18 n.5, p.1436-1445, Sept. 1997 [doi>10.1137/S1064827593255135]
	19	D. Stroobandt, "Improving Donath's Technique for Estimating the Average Interconne~on Length in Computer logic", ELIS technical report, Royal University of Ghent, June 1996.
	20	L. Trotter, "PERM (Algorithm 115)", Communications of the ACM 5 (1962).
	21	R. S. Tsay and E. Kuh, "A Unified Approach to Partitioning and Placement", IEEE Trans. on Circuits and Systems, 38(5) (1991), pp.

CITED BY 10

	Mehmet Can Yildiz , Patrick H. Madden, Global objectives for standard cell placement, Proceedings of the 11th Great Lakes symposium on VLSI, p.68-72, March 2001, West Lafayette, Indiana, United States
	Satoshi Ono , Patrick H. Madden, On structure and suboptimality in placement, Proceedings of the 2005 conference on Asia South Pacific design automation, January 18-21, 2005, Shanghai, China
	A. B. Kahng , I. Mandoiu , P. Pevzner , S. Reda , A. Zelikovsky, Engineering a scalable placement heuristic for DNA probe arrays, Proceedings of the seventh annual international conference on Research in computational molecular biology, p.148-156, April 10-14, 2003, Berlin, Germany
	Andrew B. Kahng , Sherief Reda, Placement feedback: a concept and method for better min-cut placements, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Andrew B. Kahng , Igor L. Markov , Sherief Reda, Boosting: Min-Cut Placement with Improved Signal Delay, Proceedings of the conference on Design, automation and test in Europe, p.21098, February 16-20, 2004
	Andrew E. Caldwell , Andrew B. Kahng , Igor L. Markov, Can recursive bisection alone produce routable placements?, Proceedings of the 37th conference on Design automation, p.477-482, June 05-09, 2000, Los Angeles, California, United States
	Andrew E. Caldwell , Andrew B. Kahng , Igor L. Markov, Improved algorithms for hypergraph bipartitioning, Proceedings of the 2000 conference on Asia South Pacific design automation, p.661-666, January 2000, Yokohama, Japan
	A. B. Kahng , S. Reda , Qinke Wang, Architecture and details of a high quality, large-scale analytical placer, Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design, p.891-898, November 06-10, 2005, San Jose, CA
	Shamik Das , Anantha Chandrakasan , Rafael Reif, Design tools for 3-D integrated circuits, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Shamik Das , Anantha P. Chandrakasan , Rafael Reif, Calibration of rent's rule models for three-dimensional integrated circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.12 n.4, p.359-366, April 2004