Generation of very large circuits to benchmark the partitioning of FPGA

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Generation of very large circuits to benchmark the partitioning of FPGA

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International Symposium on Physical Design archive
Proceedings of the 1999 international symposium on Physical design table of contents

Monterey, California, United States

Pages: 67 - 73

Year of Publication: 1999

ISBN:1-58113-089-9

Authors

Joachim Pistorius	Mentor Graphics Corp. Meta Systems Division, 91975 Courtaboeuf Cedex, France
Edmée Legai	Mentor Graphics Corp. Meta Systems Division, 91975 Courtaboeuf Cedex, France
Michel Minoux	Laboratoire d'Informatique, Université Pierre et Marie Curie, 75252 Paris Cedex 05, France

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 11, Citation Count: 2

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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CITED BY 2

	David Grant , Guy Lemieux, Perturb+mutate: Semisynthetic circuit generation for incremental placement and routing, ACM Transactions on Reconfigurable Technology and Systems (TRETS), v.1 n.3, p.1-24, September 2008
	Tomas Pecenka , Lukas Sekanina , Zdenek Kotasek, Evolution of synthetic RTL benchmark circuits with predefined testability, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.13 n.3, p.1-21, July 2008