Towards synthetic benchmark circuits for evaluating timing-driven CAD tools

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Towards synthetic benchmark circuits for evaluating timing-driven CAD tools

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International Symposium on Physical Design archive
Proceedings of the 1999 international symposium on Physical design table of contents

Monterey, California, United States

Pages: 60 - 66

Year of Publication: 1999

ISBN:1-58113-089-9

Authors

Dirk Stroobandt	University of Ghent, Department of Electronics and Information Systems, Belgium
Peter Verplaetse	University of Ghent, Department of Electronics and Information Systems, Belgium
Jan van Campenhout	University of Ghent, Department of Electronics and Information Systems, Belgium

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 5, Citation Count: 2

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Computer-Aided Design Benchmarking Laboratory. Web address: http://www.cbl.ncsu.edu/benchmarks/.
	2	Charles J. Alpert, The ISPD98 circuit benchmark suite, Proceedings of the 1998 international symposium on Physical design, p.80-85, April 06-08, 1998, Monterey, California, United States [doi>10.1145/274535.274546]
	3	Charles J. Alpert , Andrew B. Kahng, Recent directions in netlist partitioning: a survey, Integration, the VLSI Journal, v.19 n.1-2, p.1-81, Aug. 1995 [doi>10.1016/0167-9260(95)00008-4]
	4	Kazuo Iwama , Sunao Sawada , Kensuke Hino , Hiroyuki Kurokawa, Random Benchmark Circuits with Controlled Attributes, Proceedings of the 1997 European conference on Design and Test, p.90, March 17-20, 1997
	5	D. Ghosh , N. Kapur , J. Harlow, III , F. Brglez, Synthesis of wiring signature-invariant equivalence class circuit mutants and applications to benchmarking, Proceedings of the conference on Design, automation and test in Europe, p.656-663, February 23-26, 1998, Le Palais des Congrés de Paris, France
	6	Michael Hutton , Jonathan Rose , Derek Corneil, Generation of synthetic sequential benchmark circuits, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.149-155, February 09-11, 1997, Monterey, California, United States [doi>10.1145/258305.258333]
	7	B. S. Landman and R. L. Russo. On a pin versus block relationship for partitions of logic ~raphs. IEEE Trans. on Comput., vol. (2-20: pages 1469-1479, 1971.
	8	Joel Darnauer , Wayne Wei-Ming Dai, A method for generating random circuits and its application to routability measurement, Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays, p.66-72, February 11-13, 1996, Monterey, California, United States [doi>10.1145/228370.228380]
	9	D. Stroobandt. Generating new benchmark designs for evaluation of CAD tools and new computer architectures. Technical Report DG 98-05, University of Ghent, Belgium, ELectronics and Information Systems Department, April 1998. Available at http:llwww.elis.mg.ac.ber'dstrldstr.html.
	10	Y.-C. Wei and C.-K. Cheng. Ratio cut partitioning for hierarchical designs. IEEE Trans. Comput..Aided Des., Integrated Circuits & Syst., vol. 10 (no~ 7): pages 911-921, .luly 1991.
	11	L. Hagen, A. B. Kahng, E J. Kurdahi, and C, Ramachandran. On the intrinsic Rent parameter and spectra-based partitioning methodologies. IEEE Trans. on Comput.-Aided Des., Integrated Circuits & Syst., vol. 13 (no. 1): pages 27-37, January 1994.
	12	R.L. Russo. On the tradeoff between logic performance and circuit-to-pin ratio for LSI. IEEE Trans. Comput., vol. C- 21: pages 147-153, 1972.
	13	H. Van Marck, D. Stroobandt, and J. Van Campenhout. Towards an extension of Rent's rule for describing local vari, ations in interconnection complexity. In S. Bai, J. Fan, and X. Li, editors, Proc. 4th Intl. Conf. for Young Computer Scientists, pages 136-141. Peking University Press, 1995.
	14	E. S. Kuh and T. Ohtsuki. Recent advances in VLSI layout. Proc. of the IEEE, vol. 78: pages 237-263, 1990.
	15	Dirk Stroobandt , Fadi J. Kurdahi, On the Characterization of Multi-Point Nets in Electronic Designs, Proceedings of the Great Lakes Symposium on VLSI '98, p.344, February 19-24, 1998
	16	D. Stroobandt. Analytical methods for a priori wire length estimates in computer systems, November 1998. Ph.D. thesis (English translation from the original text in Dutch), University of Ghent, Belgium, Faculty of Applied Sciences. Available at http://www.elis.mg.ac.be/~dstr/dstr.html.

CITED BY 2

	Chin-Chih Chang , Jason Cong , Min Xie, Optimality and scalability study of existing placement algorithms, Proceedings of the 2003 conference on Asia South Pacific design automation, January 21-24, 2003, Kitakyushu, Japan
	Aditya K. Prasad , Vivek V. Shende , Igor L. Markov , John P. Hayes , Ketan N. Patel, Data structures and algorithms for simplifying reversible circuits, ACM Journal on Emerging Technologies in Computing Systems (JETC), v.2 n.4, p.277-293, October 2006