Reduction of latency and resource usage in bit-level pipelined data paths for FPGAs

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Reduction of latency and resource usage in bit-level pipelined data paths for FPGAs

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International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays table of contents

Monterey, California, United States

Pages: 227 - 234

Year of Publication: 1999

ISBN:1-58113-088-0

Authors

P. Kollig	School of Engineering and Advanced Technology, Staffordshire University, Beaconside, Stafford ST18 OAD, U.K.
B. M. Al-Hashimi	School of Engineering and Advanced Technology, Staffordshire University, Beaconside, Stafford ST18 OAD, U.K.

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 2, Downloads (12 Months): 8, Citation Count: 1

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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