Procedural texture mapping on FPGAs

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Procedural texture mapping on FPGAs

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International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays table of contents

Monterey, California, United States

Pages: 112 - 120

Year of Publication: 1999

ISBN:1-58113-088-0

Authors

Andy G. Ye	Department of Electrical and Computer Engineering, University of Toronto
David M. Lewis	Department of Electrical and Computer Engineering, University of Toronto

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 18, Citation Count: 2

Additional Information:

references cited by index terms collaborative colleagues peer to peer

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	ALTERA. Altera 1Ok FPGA Databook.
	2	BERTIN, P., ROr~CIN, D., A~rO VUmLEMIN, J. Introduction to Programmable Active Memories. Tech. rep., Digital Equipment Corporation, June 1989.
	3	BETZ, V. Architecture and CAD for Speed and Area Optimization of FPGAs. PhD thesis, University of Toronto, 1998.
	4	BUELL, D. A., AaNOLD, J. M., AND WATER, J. Splash 2: FPGAs in a custom computing machine. IEEE Computer Society Press, Los Alamos, CA, 1996.
	5	CHEREPACHA, D., AND LEWIS, D. DP-FPGA: An FPGA Architecture Optimized for Datapaths. Tech. rep., University of Toronto, 1994.
	6	David S. Ebert , F. Kenton Musgrave , Darwyn Peachey , Ken Perlin , Steven Worley, Texturing and modeling: a procedural approach, Academic Press Professional, Inc., San Diego, CA, 1994
	7	James D. Foley , Andries van Dam , Steven K. Feiner , John F. Hughes, Computer graphics: principles and practice (2nd ed.), Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1990
	8	GALLOWAY, D. 2-D Texture Mapping on TM-2. Tech. rep., University of Toronto, 1996.
	9	James Gleick, Chaos: making a new science, Penguin Books, New York, NY, 1987
	10	Randy H. Katz, Contemporary logic design, Benjamin-Cummings Publishing Co., Inc., Redwood City, CA, 1993
	11	David M. Lewis , David R. Galloway , Marcus van Ierssel , Jonathan Rose , Paul Chow, The Transmogrifier-2: a 1 million gate rapid-prototyping system, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.6 n.2, p.188-198, June 1998 [doi>10.1109/92.678867]
	12	Darwyn R. Peachey, Solid texturing of complex surfaces, ACM SIGGRAPH Computer Graphics, v.19 n.3, p.279-286, Jul. 1985
	13	Ken Perlin, An image synthesizer, ACM SIGGRAPH Computer Graphics, v.19 n.3, p.287-296, Jul. 1985
	14	RAJAMANI, S., AND VISWANATH, P. V. Accelerating the RISC processor using Programmable Logic. Tech. rep., University of Berkely, 1992.
	15	B. Ramakrishna Rau, Pseudo-randomly interleaved memory, Proceedings of the 18th annual international symposium on Computer architecture, p.74-83, May 27-30, 1991, Toronto, Ontario, Canada
	16	i~ZDAN, R. PRISC: Programmable Reduced Instruction Set Computers. PhD thesis, Harvard University, May 1994.
	17	WATANABE, Y., WONG, H., KIRIHATA, T., KATO, D., DEBROSSE, J. K., HARA, T., YOSHIDA, M., MUKAI, H., QUADEa, K. N., NAGAI, T., POECHMUELLER, P., PF~,FFERL, P., WORDEMAN, M. R., AND FUJII, S. A 286mm2 256Mb DRAM with x 32 Both-Ends DQ. IEEE Journal of Solid-State Circuits 31 (April 1996).
	18	WITTING, R. D. OneChip: an FPGA Processor with Reconfigurable Logic. Master's thesis, University of Toronto, 1995.

CITED BY 2

	Seda Ogrenci Memik , Aggelos K. Katsaggelos , Majid Sarrafzadeh, Analysis and FPGA Implementation of Image Restoration under Resource Constraints, IEEE Transactions on Computers, v.52 n.3, p.390-399, March 2003
	Xiaoying Li , Baoquan Liu , Enhua Wu, Double projective cylindrical texture mapping on FPGA, Proceedings of the 2006 ACM international conference on Virtual reality continuum and its applications, June 14-April 17, 2006, Hong Kong, China