An innovative, segmented high performance FPGA family with variable-grain-architecture and wide-gating functions

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An innovative, segmented high performance FPGA family with variable-grain-architecture and wide-gating functions

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International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays table of contents

Monterey, California, United States

Pages: 17 - 26

Year of Publication: 1999

ISBN:1-58113-088-0

Authors

Om Agrawal	Vantis Corporation, 995 Stewart Drive, Sunnyvale, CA
Herman Chang	Vantis Corporation, 995 Stewart Drive, Sunnyvale, CA
Brad Sharpe-Geisler	Vantis Corporation, 995 Stewart Drive, Sunnyvale, CA
Nick Schmitz	Vantis Corporation, 995 Stewart Drive, Sunnyvale, CA
Bai Nguyen	Vantis Corporation, 995 Stewart Drive, Sunnyvale, CA
Jack Wong	Vantis Corporation, 995 Stewart Drive, Sunnyvale, CA
Giap Tran	Vantis Corporation, 995 Stewart Drive, Sunnyvale, CA
Fabiano Fontana	Vantis Corporation, 995 Stewart Drive, Sunnyvale, CA
Bill Harding	Vantis Corporation, 995 Stewart Drive, Sunnyvale, CA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 11, Citation Count: 3

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references cited by index terms collaborative colleagues peer to peer

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Vantis VF1 Data Sheet 1998
	2	Rose, J., Francis, RJ, Lewis, D., and Chow, P. Architecture of Programmable Gate Arrays: The Effect of Logic Block Functionality on Area Efficiency. IEEE journal of Solid State Circuits, Vol. 25, No. 5, October 1990, pp. 1217-1225
	3	Stephen Brown , Muhammad Khellah , Zvonko Vranesic, Minimizing FPGA Interconnect Delays, IEEE Design & Test, v.13 n.4, p.16-23, December 1996 [doi>10.1109/54.544532]
	4	Carter, W., Duong, IC, Freman, R., Hsieh, H., Ja, J. Y., Mahoney, J. E., Ngo, N. T., and Sac, S. L. A User Programmable Reconfigurable Gate Array. Proc 1986 Custom Integrated Circuits Conference, May 1986, pp. 233-235.
	5	Hill, D., and Woo, N. S. The Benefits of Flexibility in Look-up Table FPGAs. In FPGAs, W. Moore and W. Luk Eds., Abingdon 1991. Edited from the Oxford 1991 International Workshop on Field Programmable Logic and Applications, pp. 127-136.
	6	Rose, J.S., Francis, R.J., Chow, P and Lewis, D. The Effect of Logic block Complexity on Area of Programmable Gate Arrays. Proc 1989 Custom Integrated Circuits Conference, May 1989, pp. 5.3.1 - 5.3.5
	7	Rose, J., and Brown, S. The Effect of Switch box Flexibility on Routability of Field Programmable Gate Arrays. Proc 1990 Custom Integrated Circuits Conference, pp. 27.5.1 - 27.5.4, May 1990.
	8	Vaughn Betz , Jonathan Rose, Directional bias and non-uniformity in FPGA global routing architectures, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.652-659, November 10-14, 1996, San Jose, California, United States
	9	Rose, J., and Brown, S. Flexibility of Interconnection Structures in Field Progranunable Gate Arrays. IEEE journal of Solid State Circuits, Vol 26, No. 3, pp. 277-282, March 1991.

CITED BY 3

	Elias Ahmed , Jonathan Rose, The effect of LUT and cluster size on deep-submicron FPGA performance and density, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.3-12, February 10-11, 2000, Monterey, California, United States
	Jason Meyer , Fatih Kocan, Sharing of SRAM tables among NPN-equivalent LUTs in SRAM-based FPGAs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.15 n.2, p.182-195, February 2007
	Mingjie Lin, The amorphous FPGA architecture, Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays, February 24-26, 2008, Monterey, California, USA