Hybrid product term and LUT based architectures using embedded memory blocks

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Hybrid product term and LUT based architectures using embedded memory blocks

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International Symposium on Field Programmable Gate Arrays archive
Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays table of contents

Monterey, California, United States

Pages: 13 - 16

Year of Publication: 1999

ISBN:1-58113-088-0

Authors

Frank Heile	Altera Corporation, 101 Innovation Drive, San Jose, CA
Andrew Leaver	Altera Corporation, 101 Innovation Drive, San Jose, CA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 16, Citation Count: 9

Additional Information:

references cited by index terms collaborative colleagues

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Altera Corporation, "Altera Data Book", 1998
	2	http://www.altera.com
	3	Altera Corporation, "APEX20K Data Sheet", 1999.
	4	F. Heile, "Programmable Logic Array Device with Random Access Memory Configurable as Product Terms", United States Patent Pending.
	5	Steven J. E. Wilton, SMAP: heterogeneous technology mapping for area reduction in FPGAs with embedded memory arrays, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.171-178, February 22-25, 1998, Monterey, California, United States [doi>10.1145/275107.275137]
	6	Steven Joseph Edward Wilton , Jonathan Rose , Zvenko Vranesic, Architectures and algorithms for field-programmable gate arrays with embedded memory, 1997
	7	Jason Cong , Songjie Xu, Technology mapping for FPGAs with embedded memory blocks, Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, p.179-188, February 22-25, 1998, Monterey, California, United States [doi>10.1145/275107.275138]
	8	F. Helle and A. Leaver, "Heterogeneous Technology Mapping for LUTs and Product Terms", United States Patent Pending.
	9	Alireza Kaviani , Stephen Brown, Hybrid FPGA architecture, Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays, p.3-9, February 11-13, 1996, Monterey, California, United States [doi>10.1145/228370.228371]
	10	Steven J. E. Wilton , Jonathan Rose , Zvonko G. Vranesic, Memory-to-memory connection structures in FPGAs with embedded memory arrays, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.10-16, February 09-11, 1997, Monterey, California, United States [doi>10.1145/258305.258307]
	11	S. Wilton, J. Rose and Z. Vranesic, "Memory/Logic Interconnect Flexibility in PPGAs with Large Embedded Memory Arrays," in CICC 96, the IEEE Custom Integrated Circuits Conf., San Diego, CA, May 1996, pp. 144-147.

CITED BY 9

	Alireza Kaviani , Stephen Brown, Technology mapping issues for an FPGA with lookup tables and PLA-like blocks, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.60-66, February 10-11, 2000, Monterey, California, United States
	Kenneth Yan, Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocks, Proceedings of the 2001 conference on Asia South Pacific design automation, p.231-234, January 2001, Yokohama, Japan
	Michael Hutton , Vinson Chan , Peter Kazarian , Victor Maruri , Tony Ngai , Jim Park , Rakesh Patel , Bruce Pedersen , Jay Schleicher , Sergey Shumarayev, Interconnect enhancements for a high-speed PLD architecture, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, February 24-26, 2002, Monterey, California, USA
	Gordon R. Chiu , Deshanand P. Singh , Valavan Manohararajah , Stephen D. Brown, Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs, Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design, November 05-09, 2006, San Jose, California
	Frank Heile , Andrew Leaver , Kerry Veenstra, Programmable memory blocks supporting content-addressable memory, Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays, p.13-21, February 10-11, 2000, Monterey, California, United States
	Alireza Kaviani , Stephen Brown, The Hybrid Field-Programmable Architecture, IEEE Design & Test, v.16 n.2, p.74-83, April 1999
	Somnath Paul , Swarup Bhunia, Reconfigurable computing using content addressable memory for improved performance and resource usage, Proceedings of the 45th annual conference on Design automation, June 08-13, 2008, Anaheim, California
	Michael Hutton, Interconnect prediction for programmable logic devices, Proceedings of the 2001 international workshop on System-level interconnect prediction, p.125-131, March 31-April 01, 2001, Sonoma, California, United States
	Katherine Compton , Scott Hauck, Reconfigurable computing: a survey of systems and software, ACM Computing Surveys (CSUR), v.34 n.2, p.171-210, June 2002