Functional test generation for delay faults in combinational circuits

ABSTRACT

We propose a functional fault model for delay faults in combinational circuits and describe a functional test generation procedure based on this model. The proposed method is most suitable when a gate-level description of the circuit-under-test, necessary for employing existing gate-level delay fault test generators, is not available or does not accurately describe the circuit. It is also suitable for generating tests in early design stages of a circuit, before a gate-level implementation is selected. In addition, it can potentially be employed to supplement conventional test generators for gate-level circuits to reduce the cost of handling large numbers of paths. A parameter called &Dgr; is used to control the number of funtional faults targeted and thus the number of tests generated. If &Dgr; is unlimited, the functional test set detects every robustly testable path delay fault in any gate-level implementation of the given ciruit. An appropriate subset of tests can be selected once the implentation is known. The test sets generated for various values of &Dgr; are fault simulated on gate-level realizations to demonstrate their effectiveness. The experiments indicate that functional test sets may be able to identify functions whose realizations have low path delay fault coverage.

REFERENCES

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INDEX TERMS

Primary Classification:
  B. Hardware
  B.8 Performance and Reliability

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

General Terms:
Algorithms, Design, Reliability

Keywords:
delay faults, function-robust tests, functional delay fault model, path delay faults, robust tests