Robust latch mapping for combinational equivalence checking

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Robust latch mapping for combinational equivalence checking

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 563 - 569

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

Jerry R. Burch	Cadence Berkeley Labs
Vigyan Singhal	Cadence Berkeley Labs

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 12, Citation Count: 7

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	H. Cho and C. Pixley. Apparatus and method for deriving correspondence between storage elements of a first circuit model and storage elements of a second circuit model. U. S. Patent 5,638,381. June, 1997.
	2	C. van Eijk. Formal Methods for the Verification of Digital Circuits. Ph.D. Thesis, Eindhoven University of Technology, 1997.
	3	C. A. J. van Eijk, Sequential equivalence checking without state space traversal, Proceedings of the conference on Design, automation and test in Europe, p.618-623, February 23-26, 1998, Le Palais des Congrés de Paris, France
	4	T. Filkorn. Symbolische Methoden ftir die Verifikation endlicher Zustandssysteme. Dissertation Institut ftir Informatik der Technishen Universittit Miinchen, 1992.
	5	Andreas Kuehlmann , Florian Krohm, Equivalence checking using cuts and heaps, Proceedings of the 34th annual conference on Design automation, p.263-268, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266090]
	6	Dhiraj K. Pradhan , Debjyoti Paul , Mitrajit Chatterjee, VERILAT: verification using logic augmentation and transformations, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.88-95, November 10-14, 1996, San Jose, California, United States

CITED BY 7

	Wanlin Cao , Duncan M. H. Walker , Rajarshi Mukherjee, An efficient solution to the storage correspondence problem for large sequential circuits, Proceedings of the 2001 conference on Asia South Pacific design automation, p.181-186, January 2001, Yokohama, Japan
	Kelvin Ng , Mukul R. Prasad , Rajarshi Mukherjee , Jawahar Jain, Solving the latch mapping problem in an industrial setting, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Gianpiero Cabodi , Sergio Nocco , Stefano Quer, Boosting the role of inductive invariants in model checking, Proceedings of the conference on Design, automation and test in Europe, April 16-20, 2007, Nice, France
	Demosthenes Anastasakis , Lisa McIlwain , Slawomir Pilarski, Efficient equivalence checking with partitions and hierarchical cut-points, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Demos Anastasakis , Robert Damiano , Hi-Keung Tony Ma , Ted Stanion, A practical and efficient method for compare-point matching, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Andreas Kuehlmann , Cornelis A. J. van Eijk, Combinational and sequential equivalence checking, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Yu-Chin Hsu , Furshing Tsai , Wells Jong , Ying-Tsai Chang, Visibility enhancement for silicon debug, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA