Verification of RTL generated from scheduled behavior in a high-level synthesis flow

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Verification of RTL generated from scheduled behavior in a high-level synthesis flow

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 517 - 524

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

Pranav Ashar	C&C Research Labs, NEC, Princeton, NJ
Subhrajit Bhattacharya	C&C Research Labs, NEC, Princeton, NJ
Anand Raghunathan	C&C Research Labs, NEC, Princeton, NJ
Akira Mukaiyama	C&C Research Labs, NEC, Princeton, NJ

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 3, Downloads (12 Months): 19, Citation Count: 4

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references cited by index terms collaborative colleagues peer to peer

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	J. Gong, C. T. Chen, and K. Kucukcakar, "Multi-dimensional rule checking for high-level design verification," in Proc. Int. High-level Design Validation & Test Wkshp., Nov. 1997.
	2	Reinaldo A. Bergamaschi , Salil Raje, Observable Time Windows: Verifying High-Level Synthesis Results, IEEE Design & Test, v.14 n.2, p.40-50, April 1997 [doi>10.1109/54.587740]
	3	Shin-ichi Minato, Generation of BDDs from hardware algorithm descriptions, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.644-649, November 10-14, 1996, San Jose, California, United States
	4	Raul Camposano , Wayne H. Wolf, High-Level VLSI Synthesis, Kluwer Academic Publishers, Norwell, MA, 1991
	5	Robert K. Brayton , Gary D. Hachtel , Alberto L. Sangiovanni-Vincentelli , Fabio Somenzi , Adnan Aziz , Szu-Tsung Cheng , Stephen A. Edwards , Sunil P. Khatri , Yuji Kukimoto , Abelardo Pardo , Shaz Qadeer , Rajeev K. Ranjan , Shaker Sarwary , Thomas R. Shiple , Gitanjali Swamy , Tiziano Villa, VIS: A System for Verification and Synthesis, Proceedings of the 8th International Conference on Computer Aided Verification, p.428-432, August 03, 1996
	6	R.A. Bergamaschi, "The Effects of False Paths in High-Level Synthesis," in Proc. ICCAD, Nov. 1991.
	7	J.R. Burch, E. M. Clarke, D. E. Long, K. L. McMillan, and D. L. Dill, "Symbolic model checking for sequential circuit verification," IEEE Transactions on Computer-Aided Design, vol. 13, Apr. 1994.
	8	Wolfgang Kunz, HANNIBAL: an efficient tool for logic verification based on recursive learning, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.538-543, November 07-11, 1993, Santa Clara, California, United States
	9	Chuck Monahan , Forrest Brewer, Symbolic modeling and evaluation of data paths, Proceedings of the 32nd ACM/IEEE conference on Design automation, p.389-394, June 12-16, 1995, San Francisco, California, United States [doi>10.1145/217474.217560]
	10	Robert B. Jones , David L. Dill , Jerry R. Burch, Efficient validity checking for processor verification, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.2-6, November 05-09, 1995, San Jose, California, United States
	11	Anuj Goel , Khurram Sajid , Hai Zhou , Adnan Aziz , Vigyan Singhal, BDD Based Procedures for a Theory of Equality with Uninterpreted Functions, Proceedings of the 10th International Conference on Computer Aided Verification, p.244-255, June 28-July 02, 1998

CITED BY 4

	Chandan Karfa , Dipankar Sarkar , Chittaranjan Mandal , Chris Reade, Hand-in-hand verification of high-level synthesis, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	Youngsik Kim , Nazanin Mansouri, Automated formal verification of scheduling with speculative code motions, Proceedings of the 18th ACM Great Lakes symposium on VLSI, May 04-06, 2008, Orlando, Florida, USA
	Hans Eveking , Holger Hinrichsen , Gerd Ritter, Automatic verification of scheduling results in high-level synthesis, Proceedings of the conference on Design, automation and test in Europe, p.12-es, January 1999, Munich, Germany
	Tsung-Hsi Chiang , Lan-Rong Dung, Verification method of dataflow algorithms in high-level synthesis, Journal of Systems and Software, v.80 n.8, p.1256-1270, August, 2007