Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits

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Symbolic algorithms for layout-oriented synthesis of pass transistor logic circuits

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 235 - 241

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

F. Ferrandi	Politecnico & Milano, Dip. di Elettronica e Informazione, Milano, Italy
A. Macii	Politecnico di Torino, Dip. di Automatic e Informatica Torino, Italy
E. Macii
M. Poncino	Politecnico di Torino, Dip. di Automatic e Informatica Torino, Italy
R. Scarsi	Politecnico di Torino, Dip. di Automatic e Informatica Torino, Italy
F. Somenzi	University of Colorado, Dept. of ECE, Bodder, CO

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 14, Citation Count: 6

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

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	3	K. Konishi, S. Kishimoto, B-Y. Lee, H. Tanaka, K. Taki, "A Logic Synthesis System for the Pass Transistor Logic SPL," SASIJ~fI'96, pp. 32-39, Fukuoka, Japan, November 1996.
	4	M. Tachlbana, "Heuristic Algorithm for FBDD Node Minimization with Application to Pass-Translstor Logic and DCVS Synthesis," SASI~fP96, pp. 96-101, Fukuoka, Japan, November 1996.
	5	V. Bertacco, S. Minato, P. Verplaetse, L. Benini, G. De Micheli) "Decision Diagrams and Pass Transistor Logic Synthesis/' IWLS-97, Paper 3.1, Lake Tahoe, CA, May 1997.
	6	Premal Buch , Amit Narayan , A. Richard Newton , A. Sangiovanni-Vincentelli, Logic synthesis for large pass transistor circuits, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.663-670, November 09-13, 1997, San Jose, California, United States
	7	Andreas Kuehlmann , Florian Krohm, Equivalence checking using cuts and heaps, Proceedings of the 34th annual conference on Design automation, p.263-268, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266090]
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	10	Richard L. Rudell , Alberto Sangiovanni-Vincentelli, Logic synthesis for vlsi design, 1989
	11	Ellen Sentovich , Kanwar Jit Singh , Cho W. Moon , Hamid Savoj , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli, Sequential Circuit Design Using Synthesis and Optimization, Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors, p.328-333, October 11-14, 1992
	12	F. Somenzl, GUDD: Univer~it9 of Colorado Dec~J~.on Diagram Pacicage, Release 2.1.2, Tech. Rep., Dept. of ECE, University of Colorado, Boulder, CO, April 1997.
	13	A. Grenier, F. Pecheux, ALLIANCE: A Complete Set of CAD Tools for Teaching VLSI Design, Tech. 1%ep., Laboratoire MASI/CAO-VLSI, Universit~ Pierre e Marie Curie, Pads, France, 1993.
	14	F. Brglez, H. Fujiwara, "A Neutral Netlist of 10 Combinational Benchmark Circuits and a Target Translator in Fortran," ISGAS-85, pp. 785-794, Kyoto, Japan, June 1985.

CITED BY 6

	Rudiger Ebendt , Wolfgang Gunther , Rolf Drechsler, Combination of Lower Bounds in Exact BDD Minimization, Proceedings of the conference on Design, Automation and Test in Europe, p.10758, March 03-07, 2003
	Rupesh S. Shelar , Sachin S. Sapatnekar, Recursive bipartitioning of BDDs for performance driven synthesis of pass transistor logic circuits, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	L. Macchiarulo , L. Benini , E. Macii, On-the-fly layout generation for PTL macrocells, Proceedings of the conference on Design, automation and test in Europe, p.546-551, March 2001, Munich, Germany
	Luís Guerra e Silva , L. Miguel Silveira , Joöa Marques-Silva, Algorithms for solving Boolean satisfiability in combinational circuits, Proceedings of the conference on Design, automation and test in Europe, p.107-es, January 1999, Munich, Germany
	Christoph Scholl , Bernd Becker, On the generation of multiplexer circuits for pass transistor logic, Proceedings of the conference on Design, automation and test in Europe, p.372-379, March 27-30, 2000, Paris, France
	Yanbin Jiang , Sachin S. Sapatnekar , Cyrus Bamji, Technology mapping for high-performance static CMOS and pass transistor logic designs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.5, p.577-589, October 2001