Static compaction using overlapped restoration and segment pruning

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Static compaction using overlapped restoration and segment pruning

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 140 - 146

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

Surendra K. Bommu	Computers & Communications Research Labs, NEC, Inc., Princeton, NJ
Srimat T. Chakradhar	Computers & Communications Research Labs, NEC, Inc., Princeton, NJ
Kiran B. Doreswamy	Computers & Communications Research Labs, NEC, Inc., Princeton, NJ

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 4, Citation Count: 8

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	T. M. Niermann, R. K. Roy, J. H. Patel, and J. A. Abraham, "Test compaction for sequential circuits" IEEE Trans. on CAD, vol. 11, no. 2, pp. 260-267, Feb. 1992.
	2	Byungse So, Time-efficient automatic test pattern generation systems, University of Wisconsin at Madison, Madison, WI, 1994
	3	Irith Pomeranz , Sudhakar M. Reddy, On static compaction of test sequences for synchronous sequential circuits, Proceedings of the 33rd annual conference on Design automation, p.215-220, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240558]
	4	Michael S. Hsiao , Elizabeth M. Rudnick , Janak H. Patel, Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors, Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), p.188, April 27-May 01, 1997
	5	Michael S. Hsiao , Srimat T. Chakradhar, Partitioning and Reordering Techniques for Static Test Sequence Compaction of Sequential Circuits, Proceedings of the 7th Asian Test Symposium, p.452, December 02-04, 1998
	6	R. Guo , I. Pomeranz , S. M. Reddy, Procedures for static compaction of test sequences for synchronous sequential circuits based on vector restoration, Proceedings of the conference on Design, automation and test in Europe, p.583-589, February 23-26, 1998, Le Palais des Congrés de Paris, France
	7	M. S. Hsiao , S. T. Chakradhar, State relaxation based subsequence removal for fast static compaction in sequential circuits, Proceedings of the conference on Design, automation and test in Europe, p.577-582, February 23-26, 1998, Le Palais des Congrés de Paris, France
	8	Vector restoration based static compaction of test sequences for synchronous sequential circuits, Proceedings of the 1997 International Conference on Computer Design (ICCD '97), p.360, October 12-15, 1997
	9	Anand Raghunathan , Srimat T. Chakradhar, Acceleration techniques for dynamic vector compaction, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.310-317, November 05-09, 1995, San Jose, California, United States
	10	S.T. Chakradhar and A. Raghunathan, "Bottleneck removal algorithm for dynamic compaction in sequential circuits;' IEEE Trans. on CAD, (Accepted for publication) 1997.
	11	Thomas Niermann , Janak H. Patel, HITEC: a test generation package for sequential circuits, Proceedings of the conference on European design automation, February 25-28, 1991, Amsterdam, The Netherlands
	12	E Brglez, D. Bryan, and K. Kozminski, "Combinational profiles of sequential benchmark circuits," int. Symposium on Circuits and Systems, pp. 1929-1934, May 1989.
	13	Surendra Bommu , Srimat T. Chakradhar , Kiran B. Doreswamy, Static test sequence compaction based on segment reordering and accelerated vector restoration, Proceedings of the 1998 IEEE International Test Conference, p.954, October 18-22, 1998
	14	Elizabeth M. Rudnick , Janak H. Patel, Simulation-based techniques for dynamic test sequence compaction, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.67-73, November 10-14, 1996, San Jose, California, United States
	15	T. J. Lambert , K. K. Saluja, Methods for Dynamic Test Vector compaction in Sequential Test Generation, Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication, p.166, January 03-06, 1996
	16	I. Pomeranz , S. M. Reddy, Dynamic test compaction for synchronous sequential circuits using static compaction techniques, Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96), p.53, June 25-27, 1996

CITED BY 8

	Anshuman Chandra , Krishnendu Chakrabarty, Test Resource Partitioning for SOCs, IEEE Design & Test, v.18 n.5, p.80-91, September 2001
	I. Pomeranz , S. Reddy, Sequence reordering to improve the levels of compaction achievable by static compaction procedures, Proceedings of the conference on Design, automation and test in Europe, p.214-218, March 2001, Munich, Germany
	Irith Pomeranz , Sudhakar M. Reddy, An approach for improving the levels of compaction achieved by vector omission, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.463-466, November 07-11, 1999, San Jose, California, United States
	Irith Pomeranz , Sudhakar M. Reddy, Enumeration of Test Sequences in Increasing Chronological Order to Improve the Levels of Compaction Achieved by Vector Omission, IEEE Transactions on Computers, v.51 n.7, p.866-872, July 2002
	Michael Dimopoulos , Panagiotis Linardis, Efficient Static Compaction of Test Sequence Sets through the Application of Set Covering Techniques, Proceedings of the conference on Design, automation and test in Europe, p.10194, February 16-20, 2004
	Irith Pomeranz , Sudhakar M. Reddy, Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits, IEEE Transactions on Computers, v.49 n.6, p.596-607, June 2000
	Michael S. Hsiao , Srimat Chakradhar, Test Set and Fault Partitioning Techniques for Static Test Sequence Compaction for Sequential Circuits, Journal of Electronic Testing: Theory and Applications, v.16 n.4, p.329-338, Aug.2000
	Irith Pomeranz , Sudhakar M. Reddy, A New Approach to Test Generation and Test Compaction for Scan Circuits, Proceedings of the conference on Design, Automation and Test in Europe, p.11000, March 03-07, 2003