Implementation and use of SPFDs in optimizing Boolean networks

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Implementation and use of SPFDs in optimizing Boolean networks

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 103 - 110

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

Subarnarekha Sinha	Department of Elwtricd Engineering and Computer Sciences, University of California Berkeley, CA
Robert K. Brayton	Department of Elwtricd Engineering and Computer Sciences, University of California Berkeley, CA

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 4, Downloads (12 Months): 15, Citation Count: 14

Additional Information:

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Shigeru Yamashita , Hiroshi Sawada , Akira Nagoya, A new method to express functional permissibilities for LUT based FPGAs and its applications, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.254-261, November 10-14, 1996, San Jose, California, United States
	2	Robert K. Brayton. Understanding SPFDs: A New Method for Specifying Flexibility. In IWLS, 1997.
	3	E. M. Sentovich and R. K. Brayton. Multiple Boolean Relations. In International Workshop on Logic Synthesis, Tahoe City, CA, May 1993.
	4	Ellen M. Sentovich, Vigyan Singhal, and Robert K. Brayton. Boolean Function Sets. In unpublished manuscript, 1996.
	5	H. Savoj. Improvements in Technology Independent Optimization of Logic Circuits. in IWLS, 1997.

CITED BY 15

	Subarnarekha Sinha , Andreas Kuehlmann , Robert K. Brayton, Sequential SPFDs, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Subarnarekha Sinha , Alan Mishchenko , Robert K. Brayton, Topologically constrained logic synthesis, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.679-686, November 10-14, 2002, San Jose, California
	Robert K. Brayton, The future of logic synthesis and verification, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001
	Chih-Wei Chang , Chung-Kuan Cheng , Peter Suaris , Malgorzata Marek-Sadowska, Fast post-placement rewiring using easily detectable functional symmetries, Proceedings of the 37th conference on Design automation, p.286-289, June 05-09, 2000, Los Angeles, California, United States
	R. K. Brayton, Compatible observability don't cares revisited, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California
	Balakrishna Kumthekar , Fabio Somenzi, Power and delay reduction via simultaneous logic and placement optimization in FPGAs, Proceedings of the conference on Design, automation and test in Europe, p.202-207, March 27-30, 2000, Paris, France
	Chih-Wei(Jim) Chang , Malgorzata Marek-Sadowska, Theory of wire addition and removal in combinational Boolean networks, Microelectronic Engineering, v.84 n.2, p.229-243, February, 2007
	Jason Cong , Yizhou Lin , Wangning Long, SPFD-based global rewiring, Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays, February 24-26, 2002, Monterey, California, USA
	Jason Cong , Joey Y. Lin , Wangning Long, A new enhanced SPFD rewiring algorithm, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.672-678, November 10-14, 2002, San Jose, California
	Chih-Wei Jim Chang , Malgorzata Marek-Sadowska, Who are the alternative wires in your neighborhood? (alternative wires identification without search), Proceedings of the 11th Great Lakes symposium on VLSI, p.103-108, March 2001, West Lafayette, Indiana, United States
	Catherine L. Zhou , Wai-Chung Tang , Wing-Hang Lo , Yu-Liang Wu, How much can logic perturbation help from netlist to final routing for FPGAs, Proceedings of the 44th annual conference on Design automation, June 04-08, 2007, San Diego, California
	Victor N. Kravets , Prabhakar Kudva, Implicit enumeration of structural changes in circuit optimization, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Victor N. Kravets , Karem A. Sakallah, Resynthesis of multi-level circuits under tight constraints using symbolic optimization, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.687-693, November 10-14, 2002, San Jose, California
	Jeff L. Cobb , Kanupriya Gulati , Sunil P. Khatri, Robust window-based multi-node technology-independent logic minimization, Proceedings of the 19th ACM Great Lakes symposium on VLSI, May 10-12, 2009, Boston Area, MA, USA
	Ellen Sentovich , Daniel Brand, Flexibillity in logic, Logic Synthesis and Verification, Kluwer Academic Publishers, Norwell, MA, 2001