High-level variable selection for partial-scan implementation

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High-level variable selection for partial-scan implementation

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 79 - 84

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

Frank F. Hsu	Center for Refiable & High-Performance Computing, University of Illinois, Urbana, IL
Janak H. Patel	Center for Refiable & High-Performance Computing, University of Illinois, Urbana, IL

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 5, Citation Count: 3

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Sujit Dey , Miodrag Potkonjak , Rabindra K. Roy, Exploiting hardware sharing in high-level synthesis for partial scan optimization, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.20-25, November 07-11, 1993, Santa Clara, California, United States
	2	Tien-Chien Lee , Niraj K. Jha , Wayne H. Wolf, Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments, Proceedings of the 30th international conference on Design automation, p.292-297, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164897]
	3	S. Bhatia and N. K. Jha, "Genesis: A behavioral synthesis system for hierarchical testability," in Proceedings of the IEEE European Design and Test Conference, 1994, pp. 272-276.
	4	Victor Fernandez , Pablo Sanchez, Partial Scan High-Level Synthesis, Proceedings of the 1996 European conference on Design and Test, p.481, March 11-14, 1996
	5	M. Potkonjak, S. Dey, and R. K. Roy, "Considering testability at behavioral level: use of transformations for partial scan cost minimization under timing and area constraints," IEEE Transactions on Computer- Aided Design, vol. 14, no. 5, pp. 531-546, May 1995.
	6	M. Potkonjak, S. Dey, and R. K. Roy, "Behavioral synthesis of area-efficient testable designs using interaction between hardware sharing and partial scan," IEEE Transactions on Computer-Aided Design, vol. 14, no. 9, pp. 1141-1154, September 1995.
	7	Prashant S. Parikh , Miron Abramovici, Testability-based partial scan analysis, Journal of Electronic Testing: Theory and Applications, v.7 n.1-2, p.61-70, Aug./Oct. 1995 [doi>10.1007/BF00993314]
	8	Frank F. Hsu , Elizabeth M. Rudnick , Janak H. Patel, Enhancing high-level control-flow for improved testability, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.322-328, November 10-14, 1996, San Jose, California, United States
	9	V. Chickermane and J. H. Patel, "An optimization based approach to the partial scan design problem," in Proceedings of the International Test Conference, 1990, pp. 377-386.
	10	Synopsys Reference Manual: Design Compiler, Version 1997.01, November 1996.
	11	Sunrise Tests Systems Reference Manual: Testgen and A utoloop, Version 2.3b, February 1997.

CITED BY 3

	Soheil Aminzadeh , Saeed Safari, Co-evolutionary high-level test synthesis, Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI, March 11-13, 2007, Stresa-Lago Maggiore, Italy
	Nannan He , Michael S. Hsiao, A new testability guided abstraction to solving bit-vector formula, Proceedings of the Joint Workshops of the 6th International Workshop on Satisfiability Modulo Theories and 1st International Workshop on Bit-Precise Reasoning, July 07-14, 2008, Princeton, New Jersey
	Saeed Safari , Amir Hossein Jahangir , Hadi Esmaeilzadeh, A parameterized graph-based framework for high-level test synthesis, Integration, the VLSI Journal, v.39 n.4, p.363-381, July 2006