Graph matching-based algorithms for FPGA segmentation design

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Graph matching-based algorithms for FPGA segmentation design

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 34 - 39

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

Yao-Wen Chang	Department of Computer and Information Science, National Chiao Tung University, Hsinchu 300, Taiwan
Jai-Ming Lin	Department of Computer and Information Science, National Chiao Tung University, Hsinchu 300, Taiwan
D. F. Wong	Department of Computer Sciences, University of Texas at Austin, Austin, Texas

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

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Downloads (6 Weeks): 1, Downloads (12 Months): 6, Citation Count: 0

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Actel Corporation, FPGA Data Book and Design Guide, 1996.
	2	Lucent Technologies, ORCA OR2Cz:rA (5.0 V) and OR2TxxA (3.3 V) Series Field-Programmable Gate Arrays, August 1996.
	3	A. El Gamal et al., "An Architecture for Electrically Configurable Gate Array," IEEE J. of Solid State Circuits, Vol. 24, No 2, April 1989, pp 394-398.
	4	Abbas El Gamal , Jonathan Greene , Vwani Roychowdhury, Segmented channel routing in nearly as efficient as channel routing (and just as hard), Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI, p.192-211, April 1991
	5	M. Khellah, S. Brown, and Z. Vranesic, "Minimizing interconnection delays in array-based FPGAs," in Proc. of IEEE Custom Integrated Circ. Conf., pp. 181-184, May 1994.
	6	M. J. Lorenzetti and D. S. Baeder, Chapter 5: Routing in Physical Design Automation of VLSI Systems, Edited by B. Preas and M. Lorenzetti, Benjamin/Cummings, 1988.
	7	Channel Segmentation Design for Symmetrical FPGAs, Proceedings of the 1997 International Conference on Computer Design (ICCD '97), p.496, October 12-15, 1997
	8	Christos H. Papadimitriou , Kenneth Steiglitz, Combinatorial optimization: algorithms and complexity, Prentice-Hall, Inc., Upper Saddle River, NJ, 1982
	9	M. Pedram, B. S. Nobandegani, and B.T. Preas, "Design and analysis of segmented routing channels for row-based FP- GAs," IEEE Trans. on CAD, Vol. 13, No. 12, pp. 1470-1479, Dec. 1994,
	10	Jonathan Rose , Dwight Hill, Architectural and physical design challenges for one-million gate FPGAs and beyond, Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays, p.129-132, February 09-11, 1997, Monterey, California, United States [doi>10.1145/258305.258324]
	11	K. Roy and M. Mehendale, "Optimization of Channel Segmentation for Channelled Architecture FPGAs," in Proc. of IEEE Custom Integrated Circ. Conf., pp. 4.4.1-4.4.4, May 1992.
	12	Xilinx Inc., The Programmable Logic Data Book, 1996.
	13	Kai Zhu , D. F. Wong , Yao-Wen Chang, Switch module design with application to two-dimensional segmentation design, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.480-485, November 07-11, 1993, Santa Clara, California, United States
	14	Kai Zhu , D. F. Wong, On channel segmentation design for row-based FPGAs, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.26-29, November 1992, Santa Clara, California, United States