Efficient transient electrothermal simulation of CMOS VLSI circuits under electrical overstress

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Efficient transient electrothermal simulation of CMOS VLSI circuits under electrical overstress

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International Conference on Computer Aided Design archive
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design table of contents

San Jose, California, United States

Pages: 6 - 11

Year of Publication: 1998

ISBN:1-58113-008-2

Authors

Tong Li	Analysis Product Division, Avant! Corporation
Ching-Han Tsai	Dept. of Electrical and Computer Engineering, Univ. of Illinois at Urbana-Champaign
Sung-Mo Steve Kang	Dept. of Electrical and Computer Engineering, Univ. of Illinois at Urbana-Champaign

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 16, Citation Count: 2

Additional Information:

references cited by index terms collaborative colleagues peer to peer

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	P. Yang and J. Chern, "Design for Reliability : the Major Challenge for VLSI," Proc. of the IEEE, vol.81, no.5, pp. 730-743, May 1993.
	2	C. Duvvury and A. Amerasekera, "ESD: A Pervasive Reliability Concern for IC Technologies," Proc. of the IEEE, vol. 81, no. 5, pp. 690-702, May 1993.
	3	Yi-Kan Cheng , Chin-Chi Teng , Abhijit Dharchoudhury , Elyse Rosenbaum , Sung-Mo Kang, ICET: a complete chip-level thermal reliability diagnosis tool for CMOS VLSI chips, Proceedings of the 33rd annual conference on Design automation, p.548-551, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240622]
	4	C. Diaz, S. M. Kang and C. Duvvury, "Circuit-level Electrothermal Simulation of Electrical Overstress Failures in Advanced MOS I/O Protection Devices," IEEE Trans. on CAD, vol. 13, no. 4, pp. 482--493, 1994.
	5	J. Bielefeld, G. Pelz, H. B. Abel and G. Zimmer, "Dynamic SPICE-Simulation of the Electrothermal Behavior of SOI MOS- FET's," IEEE Trans. on Electron Devices, vol. 42, no. 11, pp. 1968-1974, November, 1995.
	6	C. Diaz, C. Duwury and S. M. Kang, "Studies of EOS Susceptibility in 0.6 pm nMOS ESD I/O Protection Structures," EOS/ESD Syrup., pp. 205-211, 1993.
	7	Technology Modeling Associates, inc., Palt Alto, California, MEDICI, Two Dimensional Device Simulation Program, 1992.
	8	S. Ramaswamy, "Modeling, Simulation and Design Guidelines For EOS/ESD Protection Circuits in CMOS Technologies," Ph.D. Thesis, University of Illinois at Urbana-Champaign, 1996.
	9	A. Amerasekera, M. Chang, J. A. Seitehik, A. Chatterjee, K. Mayaram and J. Chern, " Self-Heating Effects in Basic Semiconductor Structure," IEEE Trans. on Electron Devices, Vol. 40, pp. 1836--1844, Oct., 1993.
	10	A. Amerasekera, S. Ramaswamy, M. Chang and C. Duvvury, "Modeling MOS Snapback and Parasitic Bipolar Action for Circuit-Level ESD and High Current Simulations," International Reliability Physics Symposium, pp. 318-326, 1996.
	11	P.-K. Ko, Advanced MOS Device Physics, eh. 1. Approaches to Scaling. San Francisco: Academie Press, 1989.
	12	S. Selberherr, Analysis and Simulation of Semiconductor Devices, Springer-Velag, New York, 1984.
	13	G. Krieger and P. Niles, "Diffused Resistors Characteristics at High Current Density Levels - Analysis and Applications," IEEE Trans. on Electron Devices, Vol. 36, pp. 416-423, Feb., 1989.
	14	M. N. Ozisik, Boundary Value Problems of Heat Conduction, Dover Publications, New York, 1968.
	15	G.F. Roach, Green's Function, Cambridge, 1982.
	16	V. Dwyer, A. Franklin and D. Campbell, "Thermal Failure in Semiconductor Devices," Solid State Electronics, vol. 33, no. 5, pp. 553-560, 1990.
	17	Begnaud Francis Hildebrand, Introduction to numerical analysis: 2nd edition, Dover Publications, Inc., New York, NY, 1987
	18	S. Lin , E. S. Kuh, Transient simulation of lossy interconnect, Proceedings of the 29th ACM/IEEE conference on Design automation, p.81-86, June 08-12, 1992, Anaheim, California, United States

CITED BY 2

	M. Rencz , V. Szekely , A. Poppe, A Fast Algorithm for the Layout Based Electro-Thermal Simulation, Proceedings of the conference on Design, Automation and Test in Europe, p.11032, March 03-07, 2003
	Ching-Han Tsai , Sung-Mo Kang, Fast temperature calculation for transient electrothermal simulation by mixed frequency/time domain thermal model reduction, Proceedings of the 37th conference on Design automation, p.750-755, June 05-09, 2000, Los Angeles, California, United States

INDEX TERMS

Primary Classification:
B. Hardware
B.7 INTEGRATED CIRCUITS
B.7.1 Types and Design Styles
Subjects: Memory technologies

General Terms:
Design, Experimentation, Measurement, Performance, Theory

Collaborative Colleagues:

Tong Li: colleagues

Ching-Han Tsai: colleagues

Sung-Mo Steve Kang: colleagues

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