Low threshold CMOS circuits with low standby current

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Low threshold CMOS circuits with low standby current

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International Symposium on Low Power Electronics and Design archive
Proceedings of the 1998 international symposium on Low power electronics and design table of contents

Monterey, California, United States

Pages: 97 - 99

Year of Publication: 1998

ISBN:1-58113-059-7

Author

Mircea R. Stan

University of Virginia, Electrical Engineering Department, Charlottesville, VA

Sponsors

IEEE-SSCS : Solid Stat Circuits Council
SIGDA: ACM Special Interest Group on Design Automation
IEEE-EDS : Electronic Devices Society
IEEE-CAS : Circuits & Systems

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 12, Citation Count: 3

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ABSTRACT

Multi-Voltage CMOS (MVCMOS) is a design methodology for very low power supply voltages that uses low-threshold transistors in series with the supply rails. The control voltages on the gating transistors need to be outside of the Vdd - Vss range (hence the name MVCMOS) in order to reduce the standby current, but the resulting circuits operate at lower supply voltages and have a lower area overhead than the previously proposed Multi-Threshold CMOS (MTCMOS).

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	U. Berkeley. BSIM3v3.1 SPICE MOS device models, 1997. http://www-device.EECS.Berkeley.EDU/bsim3/.
	2	J. B. Burr and A. M. Peterson. Ultra low power CMOS technology. In NASA VLSI Design Symposium, 1991.
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	4	K. Itoh, K. Sasaki, and Y. Nakagome. Trends in low-power ram circuit technologies. Proceedings of the IEEE, 83(4):524- 543, Apr. 1995.
	5	James Kao , Anantha Chandrakasan , Dimitri Antoniadis, Transistor sizing issues and tool for multi-threshold CMOS technology, Proceedings of the 34th annual conference on Design automation, p.409-414, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266182]
	6	D. Liu and C. Svensson. Trading speed for low power by choice of supply and threshold voltages. IEEE Journal of Solid-State Circuits, 28(1):10-17, Jan. 1993.
	7	Mutoh, S. et al. A 1V power supply high-speed digital circuit technology with multithreshold voltage CMOS. IEEE Journal of Solid-State Circuits, 30(8):847-854, Aug. 1995.
	8	S. Shigematsu et al. A 1-V high-speed MTCMOS circuit scheme for power-down application circuits. IEEE Journal of Solid-State Circuits, 32(6):861-869, June 1997.

CITED BY 3

	Fatih Hamzaoglu , Mircea R. Stan, Circuit-level techniques to control gate leakage for sub-100nm CMOS, Proceedings of the 2002 international symposium on Low power electronics and design, August 12-14, 2002, Monterey, California, USA
	Sung-Mo Kang, Elements of low power design for integrated systems, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea
	Benton H. Calhoun , Frank A. Honore , Anantha Chandrakasan, Design methodology for fine-grained leakage control in MTCMOS, Proceedings of the 2003 international symposium on Low power electronics and design, August 25-27, 2003, Seoul, Korea