A case study on modeling shared memory access effects during performance analysis of HW/SW systems

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

A case study on modeling shared memory access effects during performance analysis of HW/SW systems

Full text

Pdf (66 KB)

Source

International Conference on Hardware Software Codesign archive
Proceedings of the 6th international workshop on Hardware/software codesign table of contents

Seattle, Washington, United States

Pages: 117 - 121

Year of Publication: 1998

ISBN:0-8186-8442-9

Authors

Marcello Lajolo	Politecnico di Torino, Torino, Italy and NEC C&C Research Labs, Princeton, NJ
Anand Raghunathan	NEC C&C Research Labs, Princeton, NJ
Sujit Dey	UC San Diego, La Jolla, CA and NEC C&C Research Labs, Princeton, NJ
Luciano Lavagno	Politecnico di Torino, Torino, Italy
Alberto Sangiovanni-Vincentelli	University of California at Berkeley, Berkeley, CA

Sponsors

SIGSOFT: ACM Special Interest Group on Software Engineering
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IFIP : International Federation for Information Processing

Publisher

IEEE Computer Society Washington, DC, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 8, Citation Count: 8

Additional Information:

references cited by index terms collaborative colleagues peer to peer

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Kei Suzuki , Alberto Sangiovanni-Vincentelli, Efficient software performance estimation methods for hardware/software codesign, Proceedings of the 33rd annual conference on Design automation, p.605-610, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240633]
	2	B. Tabbara and L. Lavagno and A. Sangiovanni-Mncentelli, "Fast Hardware- Software Co-simulation Using Software Synthesis and Estimation," in Proc. Int. High Level Design Validation and Test Wkshp., pp. 149-I 56, Nov. 1997.
	3	Subhrajit Bhattacharya , Sujit Dey , Franc Brglez, Performance analysis and optimization of schedules for conditional and loop-intensive specifications, Proceedings of the 31st annual conference on Design automation, p.491-496, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196477]
	4	Maher Rahmouni , Ahmed A. Jerraya, Formulation and evaluation of scheduling techniques for control flow graphs, Proceedings of the conference on European design automation, p.386-391, September 18-22, 1995, Brighton, England
	5	Sujit Dey , Surendra Bommu, Performance analysis of a system of communicating processes, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.590-597, November 09-13, 1997, San Jose, California, United States
	6	Sharad Malik , Margaret Martonosi , Yau-Tsun Steven Li, Static timing analysis of embedded software, Proceedings of the 34th annual conference on Design automation, p.147-152, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266052]
	7	R. Ernst , W. Ye, Embedded program timing analysis based on path clustering and architecture classification, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.598-604, November 09-13, 1997, San Jose, California, United States
	8	Kurt Keutzer, Hardware/software co-simulation, Proceedings of the 31st annual conference on Design automation, p.439-440, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196458]
	9	"Mentor Graphics Seamless CVE Home Page (http://www.mentorg.com/seamlessn.".
	10	S. Yoo and K. Choi, "Synchronization Overhead Reduction ini Timed Cosimulation." in Proc. Int. High Level Design Volidationand Test Wkshp., pp. 157-164, Nov. 1997.
	11	James A. Rowson , Alberto Sangiovanni-Vincentelli, Interface-based design, Proceedings of the 34th annual conference on Design automation, p.178-183, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266060]
	12	Felice Balarin , Massimiliano Chiodo , Paolo Giusto , Harry Hsieh , Attila Jurecska , Luciano Lavagno , Claudio Passerone , Alberto Sangiovanni-Vincentelli , Ellen Sentovich , Kei Suzuki , Bassam Tabbara, Hardware-software co-design of embedded systems: the POLIS approach, Kluwer Academic Publishers, Norwell, MA, 1997
	13	J. Buck, S. Ha, E. Lee, and D. Masserchmitt, "Ptolemy: A framework for simulating and prototyping heterogeneous systems," International Joumol on Computer Simulation, SpecialIssue on Simulation Software Management, Jan. 1990.

CITED BY 8

	Kanishka Lahiri , Anand Raghunathan , Sujit Dey, Fast performance analysis of bus-based system-on-chip communication architectures, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.566-573, November 07-11, 1999, San Jose, California, United States
	Abhijit K. Deb , Johnny Öberg , Axel Jantsch, Control and communication performance analysis of embedded DSP systems in the MASIC methodology, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001, Montréal, P.Q., Canada
	Jong-Yeol Lee , In-Cheol Park, Timed compiled-code simulation of embedded software for performance analysis of SOC design, Proceedings of the 39th conference on Design automation, June 10-14, 2002, New Orleans, Louisiana, USA
	Abhijit K. Deb , Johnny Oberg , Axel Jantsch, Simulation and Analysis of Embedded DSP Systems Using MASIC Methodology, Proceedings of the conference on Design, Automation and Test in Europe, p.11100, March 03-07, 2003
	Marcello Lajolo, Bus guardians: an effective solution for online detection and correction of faults affecting system-on-chip buses, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.6, p.974-982, 12/1/2001
	Sungjoo Yoo , Kyoungseok Rha , Youngchul Cho , Jinyong Jung , Kiyoung Choi, Performance estimation of multiple-cache IP-based systems: case study of an interdependency problem and application of an extended shared memory model, Proceedings of the eighth international workshop on Hardware/software codesign, p.77-81, May 2000, San Diego, California, United States
	Marcello Lajolo , Anand Raghunathan , Sujit Dey, Efficient power co-estimation techniques for system-on-chip design, Proceedings of the conference on Design, automation and test in Europe, p.27-34, March 27-30, 2000, Paris, France
	Marcello Lajolo , Anand Raghunathan , Sujit Dey , Luciano Lavagno, Cosimulation-based power estimation for system-on-chip design, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.10 n.3, p.253-266, June 2002