Energy-conscious HW/SW-partitioning of embedded systems

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

Energy-conscious HW/SW-partitioning of embedded systems: a case study on an MPEG-2 encoder

Full text

Pdf (234 KB)

Source

International Conference on Hardware Software Codesign archive
Proceedings of the 6th international workshop on Hardware/software codesign table of contents

Seattle, Washington, United States

Pages: 23 - 27

Year of Publication: 1998

ISBN:0-8186-8442-9

Authors

Jouml;rg Henkel	C&C Research Laboratories, NEC USA, Princeton, NJ
Yanbing Li	Dept. of EE, Princeton University, Princeton, NJ

Sponsors

SIGSOFT: ACM Special Interest Group on Software Engineering
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CS : Computer Society
IFIP : International Federation for Information Processing

Publisher

IEEE Computer Society Washington, DC, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 15, Citation Count: 11

Additional Information:

references cited by index terms collaborative colleagues peer to peer

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Yasuhiro Nunomura , Toru Shimizu , Osamu Tomisawa, M32R/D-Integrating DRAM and Microprocessor, IEEE Micro, v.17 n.6, p.40-48, November 1997 [doi>10.1109/40.641595]
	2	Vivek Tiwari , Sharad Malik , Andrew Wolfe , Mike Tien-Chien Lee, Instruction level power analysis and optimization of software, Journal of VLSI Signal Processing Systems, v.13 n.2-3, p.223-238, Aug./Sept. 1996 [doi>10.1007/BF01130407]
	3	P-W. Ong, R.-H. Ynn, Power-Conscious Sojiware Design -a framework for modeling sojiware on hardware, IEEE F'roc. of Symposium on Low Power Electronics, pp. 36-37.1994.
	4	T. Sate, M. Nagatnatsu, H. Tago, Power and Performance Simularoc ESP and its Applicarionfor 100 MlPS/WClass RISC Design, IEEE Rot. of Symposium on Low Power Electronics, pp. 46-47,1994.
	5	T. Burd, B. Peters, A Power Ana1ysi.s of a Micmprocessoc A Study of an Implementation of the MIPS R3OOOArchitecture, Technical Report, University of California at Berkeley. May 1994.
	6	R. Gonzales. M. Horowitz, Energy Dissipation in General Purpose Pmcessors, IEEE Proc. of Symposium on Low Power Electronics, pp. 12-13.1995.
	7	Milind B. Kamble , Kanad Ghose, Analytical energy dissipation models for low-power caches, Proceedings of the 1997 international symposium on Low power electronics and design, p.143-148, August 18-20, 1997, Monterey, California, United States [doi>10.1145/263272.263310]
	8	Anand Raghunathan , Sujit Dey , Niraj K. Jha, Register-transfer level estimation techniques for switching activity and power consumption, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.158-165, November 10-14, 1996, San Jose, California, United States
	9	Inki Hong , Darko Kirovski , Miodrag Potkonjak, Potential-driven statistical ordering of transformations, Proceedings of the 34th annual conference on Design automation, p.347-352, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266161]
	10	Darko Kirovski , Miodrag Potkonjak, System-level synthesis of low-power hard real-time systems, Proceedings of the 34th annual conference on Design automation, p.697-702, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266325]
	11	Bharat P. Dave , Ganesh Lakshminarayana , Niraj K. Jha, COSYN: hardware-software co-synthesis of embedded systems, Proceedings of the 34th annual conference on Design automation, p.703-708, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266341]
	12	R.K. Gupta, G.D. MicheIi, Sysren-level Synthesis using Re-pmgmmmable Components, IEEE/ACM Pmt. of EDAC'92, pp. 2-7,1992.
	13	Frank Vahid , Daniel D. Gajski , Jie Gong, A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning, Proceedings of the conference on European design automation, p.214-219, September 19-23, 1994, Grenoble, France
	14	Peter Voigt Knudsen , Jan Madsen, PACE: A Dynamic Programming Algorithm for Hardware/Software Partitioning, Proceedings of the 4th International Workshop on Hardware/Software Co-Design, p.85, March 18-20, 1996
	15	Jörg Henkel , Rolf Ernst, A hardware/software partitioner using a dynamically determined granularity, Proceedings of the 34th annual conference on Design automation, p.691-696, June 09-13, 1997, Anaheim, California, United States [doi>10.1145/266021.266323]
	16	J. Henkel, Y Li, An Approach for Estimnring and Minimizing Energy Dissipation of Embedded ffW/SW Systems, NEC USA Inc.. Technical Report # 97-co71-4-51 lo-2,Oct.I997.
	17	S.J.E Wilton, N.P. Jouppi, An Enhanced Access and Cycle Time Model for On-Chip Caches, DEC. WRL Research Report 9315. July 1994.
	18	CORPORATE SPARC International, Inc., The SPARC architecture manual (version 9), Prentice-Hall, Inc., Upper Saddle River, NJ, 1994
	19	M. D. Hill, 1. R. Lawus, A. R. Lebeck et al., WARTS: Wisconsin Archirectuml Research Tool Set, Computer Science Department University of Wiscocnsin.
	20	K. Itoh, K. Sasaki and Y. Nakagome, Trends in Low-Power RAM Circuit Technologies, Roceedingsof the IEEE, VOL. 83, No. 4, April 1995.
	21	Prabhat K. Andleigh , Kiran Thakrar, Multimedia systems design, Prentice-Hall, Inc., Upper Saddle River, NJ, 1995
	22	V-SystemNorkFlarion User's Manual. VHDL Simulation for Worksmrions, Model Technology, 1995.
	23	R. Ernst , W. Ye, Embedded program timing analysis based on path clustering and architecture classification, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.598-604, November 09-13, 1997, San Jose, California, United States

CITED BY 11

	Matjaz Verderber , Andrej Zemva , Damjan Lampret, HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder, Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum, p.20238, March 03-07, 2003
	Roman Lysecky , Frank Vahid, Design and implementation of a MicroBlaze-based warp processor, ACM Transactions on Embedded Computing Systems (TECS), v.8 n.3, p.1-22, April 2009
	Roman Lysecky , Frank Vahid, A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning, Proceedings of the conference on Design, Automation and Test in Europe, p.18-23, March 07-11, 2005
	Greg Stitt , Roman Lysecky , Frank Vahid, Dynamic hardware/software partitioning: a first approach, Proceedings of the 40th conference on Design automation, June 02-06, 2003, Anaheim, CA, USA
	Roman Lysecky, Scalability and parallel execution of warp processing: dynamic hardware/software partitioning, International Journal of Parallel Programming, v.36 n.5, p.478-492, October 2008
	Greg Stitt , Frank Vahid , Shawn Nematbakhsh, Energy savings and speedups from partitioning critical software loops to hardware in embedded systems, ACM Transactions on Embedded Computing Systems (TECS), v.3 n.1, p.218-232, February 2004
	Brian Grattan , Greg Stitt , Frank Vahid, Codesign-extended applications, Proceedings of the tenth international symposium on Hardware/software codesign, May 06-08, 2002, Estes Park, Colorado
	Roman Lysecky , Frank Vahid, A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning, Proceedings of the conference on Design, automation and test in Europe, p.10480, February 16-20, 2004
	M. Finc , A. Zemva, Profiling soft-core processor applications for hardware/software partitioning, Journal of Systems Architecture: the EUROMICRO Journal, v.51 n.5, p.315-329, May 2005
	Greg Stitt , Frank Vahid, Hardware/software partitioning of software binaries, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design, p.164-170, November 10-14, 2002, San Jose, California
	Niraj K. Jha, Low power system scheduling and synthesis, Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design, November 04-08, 2001, San Jose, California

INDEX TERMS

Primary Classification:
C. Computer Systems Organization
C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
Subjects: Real-time and embedded systems

Additional Classification:
C. Computer Systems Organization
C.4 PERFORMANCE OF SYSTEMS
Subjects: Design studies

D. Software
D.3 PROGRAMMING LANGUAGES
D.3.2 Language Classifications

Nouns: C

General Terms:
Design, Languages, Performance

Collaborative Colleagues:

Jouml;rg Henkel: colleagues

Yanbing Li: colleagues

Peer to Peer - Readers of this Article have also read:

Constructing reality Proceedings of the 11th annual international conference on Systems documentation
Douglas A. Powell , Norman R. Ball , Mansel W. Griffiths
Data structures for quadtree approximation and compression Communications of the ACM 28, 9
Hanan Samet
A hierarchical single-key-lock access control using the Chinese remainder theorem Proceedings of the 1992 ACM/SIGAPP Symposium on Applied computing
Kim S. Lee , Huizhu Lu , D. D. Fisher
The GemStone object database management system Communications of the ACM 34, 10
Paul Butterworth , Allen Otis , Jacob Stein
Putting innovation to work: adoption strategies for multimedia communication systems Communications of the ACM 34, 12
Ellen Francik , Susan Ehrlich Rudman , Donna Cooper , Stephen Levine

Adobe Acrobat

QuickTime

Windows Media Player

Real Player