On convex formulation of the floorplan area minimization problem

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On convex formulation of the floorplan area minimization problem

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International Symposium on Physical Design archive
Proceedings of the 1998 international symposium on Physical design table of contents

Monterey, California, United States

Pages: 124 - 128

Year of Publication: 1998

ISBN:1-58113-021-X

Authors

Temo Chen	School of Electrical and Computer Engineering, Georgia Institute of Technology
Michael K. H. Fan	School of Electrical and Computer Engineering, Georgia Institute of Technology

Sponsors

IEEE-CS : Computer Society
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 22, Citation Count: 3

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ABSTRACT

It is sho wn that the floorplan area minimization problem can be formulated as a convex programming problem with the n umbers of variables and constraints significantly less than those previously published.

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Garth P. McCormick, Nonlinear programming: theory, algorithms, and applications, John Wiley & Sons, Inc., New York, NY, 1983
	2	T.-S. Mob, T.-S. Chang, and S. L. ttal6mi, Globally Optimal Floorplanning for a Layout Problem, IEEE Transaction on Circuits and Systems-I: Fundamental Theory and Applications, vol. 43, no. 9, pp. 713-720, September 1996.
	3	P. Pan and C. L. Liu, Area Minimization for Floorplans, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vo}. 14, no. 1, pp. 123-132, Ja~azy 1995.
	4	E. Rosenberg, Optimal Module Sizing in VLSI Floorplanning by Non-linear Programming, Methods Models Operations Res., voL 33, pp. 131-143, 1989.
	5	Sadiq M. Sait , Habib Youssef, VISI Physical Design Automation: Theory and Practice, McGraw-Hill, Inc., New York, NY, 1994
	6	Naveed A. Sherwani, Algorithms for VLSI Physical Design Automation, Kluwer Academic Publishers, Norwell, MA, 1995
	7	W. Shi, A Fast Algorithm for Area Minimization of Slicing Floorplans, IEEE Transactions on Computer- Aided Design of Integrated Circuits and Systems, vol. 15, no. 12, pp. 1525-1532, December 1996.
	8	Larry Stockmeyer, Optimal orientations of cells in slicing floorplan designs, Information and Control, v.57 n.2-3, p.91-101, May/June 1983 [doi>10.1016/S0019-9958(83)80038-2]
	9	S. Wimer, I. Koren, and I. Cederbaum, Floorplans, Planar Graphs, and Layouts, IEEE Transaction on Circuits and System, vol. 35, no. 3, pp. 267-278, March 1988.

CITED BY 3

	Faran Rafiq , Malgorzata Chrzanowska-Jeske , Hannah Honghua Yang , Naveed Sherwani, Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs, Proceedings of the 2002 international symposium on Physical design, April 07-10, 2002, San Diego, CA, USA
	Shih-Lian Ou , Massoud Pedram, Timing-driven placement based on partitioning with dynamic cut-net control, Proceedings of the 37th conference on Design automation, p.472-476, June 05-09, 2000, Los Angeles, California, United States
	Pinhong Chen , Ernest S. Kuh, Floorplan sizing by linear programming approximation, Proceedings of the 37th conference on Design automation, p.468-471, June 05-09, 2000, Los Angeles, California, United States