Closed form solution to simultaneous buffer insertion/sizing and wire sizing

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Closed form solution to simultaneous buffer insertion/sizing and wire sizing

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International Symposium on Physical Design archive
Proceedings of the 1997 international symposium on Physical design table of contents

Napa Valley, California, United States

Pages: 192 - 197

Year of Publication: 1997

ISBN:0-89791-927-0

Authors

Chris C. N. Chu	Department of Computer Sciences, University of Texas at Austin, Austin, TX
D. F. Wong	Department of Computer Sciences, University of Texas at Austin, Austin, TX

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 2, Downloads (12 Months): 11, Citation Count: 26

Additional Information:

references cited by index terms collaborative colleagues peer to peer

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Chung-Ping Chen , Yao-Wen Chang , D. F. Wong, Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation, Proceedings of the 33rd annual conference on Design automation, p.405-408, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240596]
	2	Chung-Ping Chen , Yao-Ping Chen , D. F. Wong, Optimal wire-sizing formula under the Elmore delay model, Proceedings of the 33rd annual conference on Design automation, p.487-490, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240611]
	3	Chung-Ping Chen and D. F. Wong. A fast algorithm for optimal wire-sizing under Elmore delay model. In Proc. IEEE ISCAS, volume 4, pages 412-415, 1996.
	4	Chung-Ping Chen , Hai Zhou , D. F. Wong, Optimal non-uniform wire-sizing under the Elmore delay model, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.38-43, November 10-14, 1996, San Jose, California, United States
	5	Chris C. N. Chu and D. F. Wong. Closed form solution to simultaneous buffer insertion/sizing and wire sizing. manuscript.
	6	Jason Cong , Lei He, An efficient approach to simultaneous transistor and interconnect sizing, Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design, p.181-186, November 10-14, 1996, San Jose, California, United States
	7	Jason Cong , Lei He, Optimal wiresizing for interconnects with multiple sources, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.1 n.4, p.478-511, Oct. 1996 [doi>10.1145/238997.239018]
	8	J. Cong , C. Koh , K. Leung, Simultaneous buffer and wire sizing for performance and power optimization, Proceedings of the 1996 international symposium on Low power electronics and design, p.271-276, August 12-14, 1996, Monterey, California, United States
	9	Jason Cong and Kwok Shing Leung. Optimal wiresizing under the distributed ti;lmore delay model. IEEE Trans. Computer-Aided Design, 14(3):321-336, March 1995.
	10	W. C. Elmore. The transient response of damped linear network with particular regard to wideband amplifiers. J. Applied Physics, 19:55-63, 1948.
	11	J. P. Fishburn and C. A. Schevon. Shaping a distributed-RC line to minimize Elmore delay. IEEE Transactions on Circuits and Systems-i: Fundamental Theory and Applications, 42(12):1020-1022, December 1995.
	12	John Lillis, Chnng-Kuan Cheng, and Ting-Ting Y. Lin. Optimal wire sizing and buffer insertion for low power and a generalized delay model. IEEE Journal of Solid State Circuits, 31(3):437-447, March 1996.
	13	Noel Menezes , Ross Baldick , Lawrence T. Pileggi, A sequential quadratic programming approach to concurrent gate and wire sizing, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.144-151, November 05-09, 1995, San Jose, California, United States
	14	Sachin S. Sapatnekar, RC interconnect optimization under the Elmore delay model, Proceedings of the 31st annual conference on Design automation, p.387-391, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196430]
	15	L. P. P. P. van Ginneken. Buffer placement in distributed RC_,-tree networks for minimal Elmore delay. In Proc. Intl. Syrup. on Circuits and Systems, pages 865- 868, 1990.
	16	Qing Zhu , Wayne W.-M. Dai , Joe G. Xi, Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.628-633, November 07-11, 1993, Santa Clara, California, United States

CITED BY 26

	Charles J. Alpert , Anirudh Devgan , Stephen T. Quay, Buffer insertion with accurate gate and interconnect delay computation, Proceedings of the 36th ACM/IEEE conference on Design automation, p.479-484, June 21-25, 1999, New Orleans, Louisiana, United States
	Subhashis Majumder , Susmita Sur-Kolay , Bhargab B. Bhattacharya , Swarup Kumar Das, Hierarchical partitioning of VLSI floorplans by staircases, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.12 n.1, p.7-es, January 2007
	C. J. Alpert , Jiang Hu , S. S. Sapatnekar , C. N. Sze, Accurate estimation of global buffer delay within a floorplan, Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, p.706-711, November 07-11, 2004
	Youxin Gao , D. F. Wong, A fast and accurate delay estimation method for buffered interconnects, Proceedings of the 2001 conference on Asia South Pacific design automation, p.533-538, January 2001, Yokohama, Japan
	Xun Liu , Yuantao Peng , Marios C. Papaefthymiou, Practical repeater insertion for low power: what repeater library do we need?, Proceedings of the 41st annual conference on Design automation, June 07-11, 2004, San Diego, CA, USA
	Yuantao Peng , Xun Liu, Power macromodeling of global interconnects considering practical repeater insertion, Proceedings of the 14th ACM Great Lakes symposium on VLSI, April 26-28, 2004, Boston, MA, USA
	Probir Sarkar , Vivek Sundararaman , Cheng-Kok Koh, Routability-driven repeater block planning for interconnect-centric floorplanning, Proceedings of the 2000 international symposium on Physical design, p.186-191, May 2000, San Diego, California, United States
	Christoph Bartoschek , Stephan Held , Dieter Rautenbach , Jens Vygen, Fast buffering for optimizing worst slack and resource consumption in repeater trees, Proceedings of the 2009 international symposium on Physical design, March 29-April 01, 2009, San Diego, California, USA
	C. J. Alpert , Miloš Hrkić , J. Hu , A. B. Kahng , J. Lillis , B. Liu , S. T. Quay , S. S. Sapatnekar , A. J. Sullivan , P. Villarrubia, Buffered Steiner trees for difficult instances, Proceedings of the 2001 international symposium on Physical design, p.4-9, April 01-04, 2001, Sonoma, California, United States
	Charles J. Alpert , Anirudh Devgan , Stephen T. Quay, Is wire tapering worthwhile?, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.430-436, November 07-11, 1999, San Jose, California, United States
	Y. Gao , D. Wong, A graph based algorithm for optimal buffer insertion under accurate delay models, Proceedings of the conference on Design, automation and test in Europe, p.535-539, March 2001, Munich, Germany
	C. C. N. Chu , D. F. Wong, A polynomial time optimal algorithm for simultaneous buffer and wire sizing, Proceedings of the conference on Design, automation and test in Europe, p.479-487, February 23-26, 1998, Le Palais des Congrés de Paris, France
	Charles J. Alpert , Anirudh Devgan , Stephen T. Quay, Buffer insertion for noise and delay optimization, Proceedings of the 35th annual conference on Design automation, p.362-367, June 15-19, 1998, San Francisco, California, United States
	Yuantao Peng , Xun Liu, Low-power repeater insertion with both delay and slew rate constraints, Proceedings of the 43rd annual conference on Design automation, July 24-28, 2006, San Francisco, CA, USA
	C. N. Sze , Jiang Hu , Charles J. Alpert, A place and route aware buffered Steiner tree construction, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair, p.355-360, January 27-30, 2004, Yokohama, Japan
	Chris C. N. Chu , D. F. Wong, A new approach to simultaneous buffer insertion and wire sizing, Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design, p.614-621, November 09-13, 1997, San Jose, California, United States
	Xun Liu , Yuantao Peng , Marios C. Papaefthymiou, RIP: An Efficient Hybrid Repeater Insertion Scheme for Low Power, Proceedings of the conference on Design, Automation and Test in Europe, p.1330-1335, March 07-11, 2005
	Yuantao Peng , Xun Liu, A sensitivity analysis of low-power repeater insertion, Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 17-19, 2005, Chicago, Illinois, USA
	Chris Chu , D. F. Wong, Closed form solutions to simultaneous buffer insertion/sizing and wire sizing, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.3, p.343-371, July 2001
	Xiaoping Tang , D. F. Wong, Planning buffer locations by network flows, Proceedings of the 2000 international symposium on Physical design, p.180-185, May 2000, San Diego, California, United States
	Christoph Bartoschek , Stephan Held , Dieter Rautenbach , Jens Vygen, Efficient generation of short and fast repeater tree topologies, Proceedings of the 2006 international symposium on Physical design, April 09-12, 2006, San Jose, California, USA
	Sebastian Vogel , Martin D. F. Wong, Closed form solution for optimal buffer sizing using the Weierstrass elliptic function, Proceedings of the 2006 conference on Asia South Pacific design automation, January 24-27, 2006, Yokohama, Japan
	Yuantao Peng , Xun Liu, Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method, Proceedings of the 42nd annual conference on Design automation, June 13-17, 2005, San Diego, California, USA
	Subhas C. Nandy , Bhargab B. Bhattacharya, On finding an empty staircase polygon of largest area (width) in a planar point-set, Computational Geometry: Theory and Applications, v.26 n.2, p.143-171, October 2003
	Jason Cong , Tianming Kong , David Zhigang Pan, Buffer block planning for interconnect-driven floorplanning, Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, p.358-363, November 07-11, 1999, San Jose, California, United States
	Jason Cong , Tianming Kong , Zhigang (David) Pan, Buffer block planning for interconnect planning and prediction, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.9 n.6, p.929-937, 12/1/2001

INDEX TERMS

Primary Classification:
B. Hardware
B.7 INTEGRATED CIRCUITS
B.7.1 Types and Design Styles
Subjects: VLSI (very large scale integration)

Additional Classification:
B. Hardware
B.4 INPUT/OUTPUT AND DATA COMMUNICATIONS

C. Computer Systems Organization
C.1 PROCESSOR ARCHITECTURES
C.1.2 Multiple Data Stream Architectures (Multiprocessors)
Subjects: Interconnection architectures (e.g., common bus, multiport memory, crossbar switch)

General Terms:
Design, Measurement, Performance, Theory, Verification

Collaborative Colleagues:

Chris C. N. Chu: colleagues

D. F. Wong: colleagues

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