Minimization of chip size and power consumption of high-speed VLSI buffers

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Minimization of chip size and power consumption of high-speed VLSI buffers

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International Symposium on Physical Design archive
Proceedings of the 1997 international symposium on Physical design table of contents

Napa Valley, California, United States

Pages: 186 - 191

Year of Publication: 1997

ISBN:0-89791-927-0

Authors

D. Zhou	The Department of Electrical Engineering, UNCC, Charlotte, NC
X. Y. Liu	The Department of Electrical Engineering, UNCC, Charlotte, NC

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 10, Citation Count: 4

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Carver Mead , Lynn Conway, Introduction to VLSI Systems, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1979
	2	ll.B. Bakoglu, Circuits, Interconnections and packag- Lug for VLSI, Addison-Wesley, 1990.
	3	D. Zhou, F.P. Preparata, and S.M. Kang, "Interconnection delay in Very High-Speed VLSI," IEEE Trans. Circuits Systems, VOL. 38, 1991.
	4	Douglas A. Pucknell , Kamran Eshraghian, Basic VLSI design: systems and circuits, 2nd ed., Prentice-Hall, Inc., Upper Saddle River, NJ, 1988
	5	Neil H. E. Weste , Kamran Eshraghian, Principles of CMOS VLSI design: a systems perspective, Addison-Wesley Longman Publishing Co., Inc., Boston, MA, 1985
	6	D. Zhou, F. Tsui, D.S. Gao and J.S. Cong, ~A distributed-RLC model for MCM layout," Proc. IEEE Multichip Module ConL, 1993.
	7	D. Zhou , S. Su , F. Tsui , D. S. Gao , J. S. Cong, A simplified synthesis of transmission lines with a tree structure, Analog Integrated Circuits and Signal Processing, v.5 n.1, p.19-30, Jan. 1994 [doi>10.1007/BF01673903]
	8	Chen-Ping Yuan, "Modelling and extraction of interconnection P parameters in VLSI", 1983
	9	Jason Cong , Cheng-Kok Koh, Simultaneous driver and wire sizing for performance and power optimization, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.408-425, Dec. 1994 [doi>10.1109/92.335010]
	10	Farid N. Najm, A survey of power estimation techniques in VLSI circuits, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.2 n.4, p.446-455, Dec. 1994 [doi>10.1109/92.335013]
	11	A.P. Chandr "akasan, S. Sheng, and R. W. Brodersn, "Low-power CMOS digital design," IEEE J. Solid- State Circ., Vol. 27, No. 4, PP. 473-484, April 1992
	12	S. Devadas, K. Keutzer, and J. White, "Estimation of power dissipation in CMOS combinational circuits using Boolean function manipulation," IEEE Trans. Computer-Aided Design, Vol. 11, No. 3, PP. 373-383, March 1992
	13	U. Jagan, "SIMCURRENT- An efficient program for the estimation of the current flow of complex CMOS circuits," IEEE Int. Conf. Computer-Aided Design, Santa Clara, CA, Nov. 11-15, 1990, pp. 396-399
	14	M. A. Cirit, "Estimaing dynamic power consumption of CMOS circuits," IEEE Int. Conf. Computer-Aided Design, Nov. 9-12, pp. 534-537, 1987
	15	D. Zhou and X.Y. Liu "On the Optimal Drivers of High-Speed Low Power ICs", to appear in International Journal of High-speed Electronics and Systems, Vol. 7, No. 2, June 1996.
	16	Jan M. Rabaey, Digital integrated circuits: a design perspective, Prentice-Hall, Inc., Upper Saddle River, NJ, 1996
	17	Philip E. Gill and et. al., "Practical Optimization", Academic Press, 1981.
	18	N. Hedenstiern et al., "CMOS Circuit Speed and Buffer Optimization", IEEE Trans. on Computer-Aided Design, Vol. CAD-6, No. 2, pp.270-281, March 1987.

CITED BY 4

	Behnam Amelifard , Farzan Fallah , Massoud Pedarm, Low-power fanout optimization using MTCMOS and multi-Vt techniques, Proceedings of the 2006 international symposium on Low power electronics and design, October 04-06, 2006, Tegernsee, Bavaria, Germany
	Ruiming Li , Dian Zhou , Jin Liu , Xuan Zeng, Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing, Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design, p.581, November 09-13, 2003
	Chris Chu , D. F. Wong, Closed form solutions to simultaneous buffer insertion/sizing and wire sizing, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.3, p.343-371, July 2001
	Dian Zhou , Rui-Ming Li, Design and verification of high-speed VLSI physical design, Journal of Computer Science and Technology, v.20 n.2, p.147-165, March 2005