EWA

Subscribe (Full Service)


	Search: The ACM Digital Library The Guide

	Feedback

EWA: exact wiring-sizing algorithm

Full text

Pdf (1.11 MB)

Source

International Symposium on Physical Design archive
Proceedings of the 1997 international symposium on Physical design table of contents

Napa Valley, California, United States

Pages: 178 - 185

Year of Publication: 1997

ISBN:0-89791-927-0

Authors

Rony Kay	Carnegie Mellon University, Department of Electrical and Computer Engineering, Pittsburgh, PA
Gennady Bucheuv	Carnegie Mellon University, Department of Electrical and Computer Engineering, Pittsburgh, PA
Lawrence T. Pileggi	Carnegie Mellon University, Department of Electrical and Computer Engineering, Pittsburgh, PA

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 1, Citation Count: 3

Additional Information:

references cited by index terms collaborative colleagues peer to peer

Tools and Actions:	Review this Article Save this Article to a Binder Display Formats: BibTeX EndNote ACM Ref

DOI Bookmark:	Use this link to bookmark this Article: http://doi.acm.org/10.1145/267665.267710 What is a DOI?

REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Chung-Ping Chen , Yao-Ping Chen , D. F. Wong, Optimal wire-sizing formula under the Elmore delay model, Proceedings of the 33rd annual conference on Design automation, p.487-490, June 03-07, 1996, Las Vegas, Nevada, United States [doi>10.1145/240518.240611]
	2	Jason Cong , Lei He , Cheng-Kok Koh , Patrick H. Madden, Performance optimization of VLSI interconnect layout, Integration, the VLSI Journal, v.21 n.1-2, p.1-94, Nov. 1996 [doi>10.1016/S0167-9260(96)00008-9]
	3	Jason Cong , Kwok-Shing Leung, Optimal wiresizing under the distributed Elmore delay model, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.634-639, November 07-11, 1993, Santa Clara, California, United States
	4	J. Cong and K.-S. Leung, "Optimal wiresizing under Elmore delay model," IEEE Trans. Computer-Aided Design, 140), pp. 321-336, March 1995.
	5	J, G. Eeker, "Geometric programming: methods, computations and applications," SIAM Review, 22, pp. 338-362, July 1980.
	6	W. C, Elmore. "The transient response of damped linear networks with particular regard to wide-band amplifiers," J. Applied Physics, 19(1), pp. 55-63, Jan. 1948.
	7	J. E Fishbum and A. E. Durdop, "TII~S: A posynomial programming approach to transistor sizing," Proc. of the Intl. Conf. on Computer.Aided Design, pp. 326--328, Nov. 1985.
	8	J. E Fishburn and C.A. Schevon, "Shaping a Distributed- RC Line to Minimize Elmore Delay," IEEE Trans. on Circuits and Systems, 42(12), pp. 1020-1022, December 1995.
	9	J.Y. Lee, X Huang, and R. Rohrer, "Pole and zero sensitivity calculation in asymptotic waveform evaluation," IEEE Trans. Computer-Aided Design, H(5), pp. 586-597, May 1992.
	10	Noel Menezes , Satyamurthy Pullela , Florentin Dartu , Lawrence T. Pillage, RC interconnect synthesis—a moment fitting approach, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.418-425, November 06-10, 1994, San Jose, California, United States
	11	Noel Menezes , Ross Baldick , Lawrence T. Pileggi, A sequential quadratic programming approach to concurrent gate and wire sizing, Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design, p.144-151, November 05-09, 1995, San Jose, California, United States
	12	E Penfield, J. Rubinstein, and M. Horowitz, "Signal delay in RC tree networks," IEEE Trans. Computer-Aided Design, CAD.2, pp. 202-211, July 1983.
	13	L.T. Pillage and R. Rohrer, "Asymptotic waveform evaluation for timing analysis," IEEE Trans. Computer-Aided Design, 9(4), pp. 352-366, April 1990.
	14	Satyamurthy Pullela , Noel Menezes , Lawrence T. Pillage, Reliable non-zero skew clock trees using wire width optimization, Proceedings of the 30th international conference on Design automation, p.165-170, June 14-18, 1993, Dallas, Texas, United States [doi>10.1145/157485.164653]
	15	S. Pullela, N. Menezes and L.T. Pileggi, Clock Skew Minimization via wire Width Optimization, IEEE Transactions on Computer-Aided Design, Accepted for Publication.
	16	C. Ratzlaffaad L. T. Pillage, "RICE: rapid interconnect circuit evaluation using AWE," IEEE Trans. Computer.Aided Design, 13(6), pp. 763-776, June 1994.
	17	S.S. Sapatnekar, V. B. Rao, R M. Vaidya, and S.-M. Kang, "An exact solution to the transistor sizing problem for CMOS circuits using convex optimization," IEEE Trans. Computer-Aided Design, 12(11), pp. 1621- 1634, May 1992.
	18	Sachin S. Sapatnekar, RC interconnect optimization under the Elmore delay model, Proceedings of the 31st annual conference on Design automation, p.387-391, June 06-10, 1994, San Diego, California, United States [doi>10.1145/196244.196430]
	19	S.S. Sapatnekar, "Wire Sizing as a Convex Optimization Problem: Exploring the Area-Delay Tradeoff," IEEE Trans. Computer-AidedDesign, 15(8), pp. 1001- 1011,Aug. 1996.
	20	R-S. Tsay, "F.,xact Zero.skew", pp. 336-339, Proc. IEEE International Conference on Computer-Aided Design, Nov 1991.
	21	Qing Zhu , Wayne W.-M. Dai , Joe G. Xi, Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models, Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design, p.628-633, November 07-11, 1993, Santa Clara, California, United States

CITED BY 3

	Jeng-Liang Tsai , Tsung-Hao Chen , Charlie Chung-Ping Chen, Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time, Proceedings of the 2003 international symposium on Physical design, April 06-09, 2003, Monterey, CA, USA
	Zhaoyun Xing , Prithviraj Banerjee, A parallel algorithm for zero skew clock tree routing, Proceedings of the 1998 international symposium on Physical design, p.118-123, April 06-08, 1998, Monterey, California, United States
	Chris Chu , D. F. Wong, Closed form solutions to simultaneous buffer insertion/sizing and wire sizing, ACM Transactions on Design Automation of Electronic Systems (TODAES), v.6 n.3, p.343-371, July 2001