Regular layout generation of logically optimized datapaths

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Regular layout generation of logically optimized datapaths

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International Symposium on Physical Design archive
Proceedings of the 1997 international symposium on Physical design table of contents

Napa Valley, California, United States

Pages: 42 - 47

Year of Publication: 1997

ISBN:0-89791-927-0

Authors

R. X. T. Nijssen	Eindhoven University of Technology, Department of Electrical Engineering/ICS EH9.28, P.O. Box 513, 5600MB, Eindhoven, The Netherlands
C. A. J. van Eijk	Eindhoven University of Technology, Department of Electrical Engineering/ICS EH9.28, P.O. Box 513, 5600MB, Eindhoven, The Netherlands

Sponsor

SIGDA: ACM Special Interest Group on Design Automation

Publisher

ACM New York, NY, USA

Bibliometrics

Downloads (6 Weeks): 1, Downloads (12 Months): 6, Citation Count: 3

Additional Information:

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REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

	1	Daniel Brand , Anthony Drumm , Sandip Kundu , Prakash Narain, Incremental synthesis, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.14-18, November 06-10, 1994, San Jose, California, United States
	2	Randal E. Bryant, Graph-based algorithms for Boolean function manipulation, IEEE Transactions on Computers, v.35 n.8, p.677-691, Aug. 1986 [doi>10.1109/TC.1986.1676819]
	3	C. A. J. van Eijk , Geert Janssen, Exploiting Structural Similarities in a BDD-Based Verification Method, Proceedings of the Second International Conference on Theorem Provers in Circuit Design - Theory, Practice and Experience, p.110-125, September 26-28, 1994
	4	C.A.J. van Eijk and J.A.G. Jess. Detection of Equivalent State Variables in Finite State Machine Verification. Workshop notes of the 1995 ACM/IEEE Int. Workshop on Logic Synthesis, pp. 3.35-3.44, 1995.
	5	R.X.T. Nijssen and J.A.G. Jess. Two-Dimensional Datapath Regularity Extraction. Workshop notes of the 5th ACM/SIGDA Physical Design Workshop, pp. ! 10-117, 1996.
	6	G. Odawara, T. Hiraide and O. Nishina. Partitioning and Placement Technique for CMOS Gate Array. IEEE Trans. on Computer Aided Design, voh 6, no. 3, pp. 355-363, 1987.

CITED BY 3

	Terry Tao Ye , Giovanni De Micheli, Data path placement with regularity, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California
	Amit Chowdhary , Sudhakar Kale , Phani Saripella , Naresh Sehgal , Rajesh Gupta, A general approach for regularity extraction in datapath circuits, Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design, p.332-339, November 08-12, 1998, San Jose, California, United States
	Thomas Kutzschebauch , Leon Stok, Regularity driven logic synthesis, Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design, November 05-09, 2000, San Jose, California