Achievable bounds on signal transition activity

ABSTRACT

Transitions on high capacitance busses in VLSI systems result in considerable system power dissipation. Therefore, various coding schemes have been proposed in the literature to encode the input signal in order to reduce the number of transitions. In this paper we derive achievable lower and upper bounds on the expected signal transition activity. These bounds are derived via an information-theoretic approach in which symbols generated by a source (possibly correlated) with entropy rate H are coded with an average of R bits/symbol. These results are applied to, 1.) determine the activity reducing efficiency of different coding algorithms such as Entropy coding, Transition coding, and Bus-Invert coding, 2.) bound the error in entropy-based power estimation schemes, and 3.) determine the lower-bound on the power-delay product. Two examples are provided where transition activity within 4% and 8% of the lower bound is achieved when blocks of 8 and 13 symbols respectively are coded at a time.

REFERENCES

• 1: Thomas M. Cover , Joy A. Thomas, Elements of information theory, Wiley-Interscience, New York, NY, 1991
• 2: D. Marculescu, R. Marculescu, and M. Pedram, "Information theoretic measures for power analysis," IEEE Trans. CAD, pp. 599-610, June 1996.
• 3: M. Nemani and F. Najm, "Towards a High-Level Power Estimation Capability," IEEE Trans. CAD, pp. 588- 598, June 1996.
• 4: Sumant Ramprasad , Naresh R. Shanbhag , Ibrahim N. Hajj, Information-theoretic bounds on average signal transition activity, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.7 n.3, p.359-368, Sept. 1999 [doi>10.1109/92.784097]
• 5: N. R. Shanbhag, "A mathematical basis for powerreduction in digital VLSI systems," IEEE Trans. CAS H (to appear).
• 6: Mircea R. Stan , Wayne P. Burleson, Bus-invert coding for low-power I/O, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.3 n.1, p.49-58, March 1995 [doi>10.1109/92.365453]

INDEX TERMS

Primary Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS
      B.7.1 Types and Design Styles
          Subjects: VLSI (very large scale integration)

Additional Classification:
  C. Computer Systems Organization
  C.1 PROCESSOR ARCHITECTURES
      C.1.2 Multiple Data Stream Architectures (Multiprocessors)
          Subjects: Interconnection architectures (e.g., common bus, multiport memory, crossbar switch)
  C.3 SPECIAL-PURPOSE AND APPLICATION-BASED SYSTEMS
      Subjects: Signal processing systems

  I. Computing Methodologies
  I.5 PATTERN RECOGNITION
      I.5.4 Applications
          Subjects: Signal processing

General Terms:
Algorithms, Design, Measurement, Performance, Theory, Verification

Keywords:
Low power, switching activity, achievable bounds, CMOS circuits, information theory, busses, power estimation