ACM Home Page
Please provide us with feedback. Feedback
Disjunctive partitioning and partial iterative squaring: an effective approach for symbolic traversal of large circuits
Full text PdfPdf (384 KB)
Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 34th annual Design Automation Conference table of contents
Anaheim, California, United States
Pages: 728 - 733  
Year of Publication: 1997
ISBN:0-89791-920-3
Authors
Gianpiero Cabodi  Politecnico di Torino, Dip. di Automatica e Informatica, Turin, Italy
Paolo Camurati  Università di Udine Dip. di Matematica e Informatica, Udine, Italy
Luciano Lavagno  Politecnico di Torino, Dip. di Elettronica, Turin, Italy
Stefano Quer  Politecnico di Torino, Dip. di Automatica e Informatica, Turin, Italy
Sponsors
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
Bibliometrics
Downloads (6 Weeks): 1,   Downloads (12 Months): 13,   Citation Count: 23
Additional Information:

abstract   references   cited by   index terms   collaborative colleagues   peer to peer  

Tools and Actions: Request Permissions Request Permissions    Review this Article  
DOI Bookmark: Use this link to bookmark this Article: http://doi.acm.org/10.1145/266021.266355
What is a DOI?

ABSTRACT

Extending the applicability of reachability analysis to large andreal circuits is a key issue.In fact they are still limited forthe following reasons: peak BDD size during image computation,BDD explosion for representing state sets and very highsequential depth.Following the promising trend of partitioning and problem decomposition,we present a new approach based on a disjunctivepartitioned transition relation and on an improved iterativesquaring.In this approach a Finite State Machine is decomposedand traversed one "functioning-mode" at a time bymeans of the "disjunctive" partitioned approach.The overall algorithm aims at lowering the intermediate peakBDD size pushing further reachability analysis.Experimentson a few industrial circuits containing counters and on somelarge benchmarks show the feasibility of the approach.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
1
 
2
 
3
J.R. Butch, E.M. Clarke, D.E. Long, K.L. McMillan, D.L. Dill: "Symbolic Model Checking for Sequential Circuit Verification," lEEE-Trar~saction on CAD, pp. 401-424, Volume 13, Number 4, April 1994
4
 
5
 
6
H. Cho, G.D. I-Iachtel, E. Macii, M. Poncino, K. Ravi, F. Somenzi, "Approximate Finite State Machine Traversal: Extensions and New Results," in Proc. IWLS'95, May 1995
 
7
M68HCll Reference Manual, Motorola inc., 1991
 
8

CITED BY  23
 
 
 
 
 
 

Collaborative Colleagues:
Gianpiero Cabodi: colleagues
Paolo Camurati: colleagues
Luciano Lavagno: colleagues
Stefano Quer: colleagues

Peer to Peer - Readers of this Article have also read: