ATPG for heat dissipation minimization during scan testing

ABSTRACT

An ATPG technique is proposed that reduces heat dissipationduring testing of sequential circuits that have full-scan. The objectiveis to permit safe and inexpensive testing of low power circuitsand bare die that would otherwise require expensive heat removalequipment for testing at high speeds. The proposed ATPG exploitsall don't cares that occur during scan shifting, test application, andresponse capture to minimize switching activity in the circuit undertest. Furthermore, an ATPG that maximizes the number of state inputsthat are assigned don't care values, has been developed. Theproposedtechniquehas beenimplemented and usedto generatetestsfor full scan versions of ISCAS 89 benchmark circuits. These testsdecrease the average number of transitions during test by 19% to89%, when comparedwith those generatedby a simple PODEM implementation.

REFERENCES

• ABF90: M. Abramovici, M. A. Breuer, and A. D. Friedman. Digital Systems Testing and Testable Design. Computer Science Press, New York, N.Y., 1990.
• AKR91: Miron Abramovici , James J. Kulikowski , Rabindra K. Roy, The Best Flip-Flops to Scan, Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner, p.166-173, October 26-30, 1991
• Goe81: E Goel. An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits. IEEE Trans. on Computers, Vol. C-30(3), March 1981.
• Kee92: D.C. Keezer. Bare Die Testing and MCM Probing Techniques. In ProceedingsMulti Chip Module Conference, pages 20-23, March 1992.
• KL70: B.W. Kernighan and S. Lin. An Efficient Heuristic Procedure for Partitioning Graphs. Bell System Techniacl Journal, 49:291-307, Febrary 1970.
• Par92: R.H. Parker. Bare Die Test. In ProceedingsMulti Chip Module Conference, pages 24-27, March 1992.
• SGDK92: Amelia Shen , Abhijit Ghosh , Srinivas Devadas , Kurt Keutzer, On average power dissipation and random pattern testability of CMOS combinational logic networks, Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design, p.402-407, November 1992, Santa Clara, California, United States
• TPCD94: Chi-Ying Tsui , Massoud Pedram , Chih-Ang Chen , Alvin M. Despain, Low power state assignment targeting two-and multi-level logic implementations, Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design, p.82-87, November 06-10, 1994, San Jose, California, United States
• WG94: Seongmoon Wang , Sandeep K. Gupta, ATPG for Heat Dissipation Minimization During Test Application, Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years, p.250-258, October 02-06, 1994
• WG96: S. Wang and S. K. Gupta. ATPG for Heat Dissipation for Scan Testing. University of Southern California Computer Engneering Technical Report 96-22, 1996.
• Zor: Y. Zorian. Private Communication.
• Zor93: Y. Zorian. A Distributed BIST Control Scheme for Complex VLSI Devices. In Proceedings VLSI Testing Symposium, pages 4-9, 1993.

INDEX TERMS

Primary Classification:
  C. Computer Systems Organization

Additional Classification:
  B. Hardware
  B.7 INTEGRATED CIRCUITS

  G. Mathematics of Computing
  G.4 MATHEMATICAL SOFTWARE
      Subjects: Algorithm design and analysis

  K. Computing Milieux
  K.6 MANAGEMENT OF COMPUTING AND INFORMATION SYSTEMS
      K.6.2 Installation Management
          Subjects: Benchmarks

General Terms:
Algorithms, Design, Measurement, Performance, Reliability, Standardization, Theory