Hierarchical test generation and design for testability of ASPPs and ASIPs

ABSTRACT

In this paper, we present design for testability (DFT) and hierarchicaltest generation techniques for facilitating the testingof application-specific programmable processors (ASPPs) andapplication-specific instruction processors (ASIPs). The methodutilizes the register transfer level (RTL) circuit description of anASPP or ASIP and tries to generate a set of test microcode patternswhich can be written into the instruction read-only memory(ROM) of the processor. These lines of microcode dictate a newcontrol/data flow in the circuit and can be used to test moduleswhich are not easily testable. The new control/data flow is used tojustify precomputed test sets of a module from the system primaryinputs to the module inputs and propagate output responses fromthe module output to the system primary outputs. If the derived testmicrocode cannot test all untested modules in the circuit, then testmultiplexers are added to the data path to test these modules andthus testability of all modules is guaranteed. This scheme has theadvantages of low area and delay overheads (average of 3.1% and0.4% respectively), high fault coverage (>99.6% for all cases) andat-speed testing. Test generation times are about three orders ofmagnitude smaller than an efficient gate-level sequential test generator.Only one external test pin is required for the DFT method.

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INDEX TERMS

Primary Classification:
  C. Computer Systems Organization

Additional Classification:
  B. Hardware
  B.5 REGISTER-TRANSFER-LEVEL IMPLEMENTATION
  B.7 INTEGRATED CIRCUITS

General Terms:
Design, Experimentation, Measurement, Performance, Theory