| SWITTEST: automatic switch-level fault simulation and test evaluation of switched-capacitor systems |
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Annual ACM IEEE Design Automation Conference
archive
Proceedings of the 34th annual Design Automation Conference
table of contents
Anaheim, California, United States
Pages: 281 - 286
Year of Publication: 1997
ISBN:0-89791-920-3
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Authors
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S. Mir
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Instituto de Microelectrónica de Sevilla, Centro Nacional de Microelectrónica, Edif. CICA, Av. Reina Mercedes, 41012 Sevilla, Spain
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A. Rueda
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Instituto de Microelectrónica de Sevilla, Centro Nacional de Microelectrónica, Edif. CICA, Av. Reina Mercedes, 41012 Sevilla, Spain
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T. Olbrich
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AMS - Austria Mikro Systeme Int. AG, Concept Engineering & Application, Schloss Premstaetten, A-8141 Unterpremstaetten, Austria
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E. Peralías
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Instituto de Microelectrónica de Sevilla, Centro Nacional de Microelectrónica, Edif. CICA, Av. Reina Mercedes, 41012 Sevilla, Spain
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J. L. Huertas
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Instituto de Microelectrónica de Sevilla, Centro Nacional de Microelectrónica, Edif. CICA, Av. Reina Mercedes, 41012 Sevilla, Spain
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Downloads (6 Weeks): 1, Downloads (12 Months): 7, Citation Count: 3
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ABSTRACT
A tool for the switch-level fault simulation and test evaluationof switched-capacitor systems is presented. Time or frequency-domainfault simulations with SWITCAP and time-domain faultsimulations with HSPICE can be performed. Adequate fault modelsare presented for both simulators. The tool has proven to bevery useful in the early evaluation of test strategies, providing similarresults to those obtained at the transistor-level.
REFERENCES
Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.
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Meta-Software Inc. HSPICE User's Manual, 1995.
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K. Suyama, S.C. Fang, and Y.E Tsividis. Simulation of mixed switchedcapacitor/digital networks with signal-driven switches. IEEE Journal of Solid- State Circuits, SC-25(6): 1403-1413, December 1990.
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I.M. Bell and S.J. Spinks. Analogue fault simulation for the structural approach to analogue and mixed-signal IC testing. In IEEE International Mixed Signal Testing Workshop, pages 10-14, Villard-de-Lans, France, June 1995.
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S. Mir, M. Lubaszewski, and B. Courtois. Fault-based ATPG for linear analogue circuits with minimal size multifrequency test sets. Journal of Elect~vnic Testing: Theory and Applications, 9(1/2) :43-57, August/October 1996.
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CITED BY 3
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S. Mir , A. Rueda , D. Vázquez , J. L. Huertas, Switch-level fault coverage analysis for switch-capacitor systems, Proceedings of the conference on Design, automation and test in Europe, p.810-814, February 23-26, 1998, Le Palais des Congrés de Paris, France
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