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Rapid frequency-domain analog fault simulation under parameter tolerances
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Source Annual ACM IEEE Design Automation Conference archive
Proceedings of the 34th annual Design Automation Conference table of contents
Anaheim, California, United States
Pages: 275 - 280  
Year of Publication: 1997
ISBN:0-89791-920-3
Authors
Michael W. Tian  Department of Electrical and Computer Engineering, University of Iowa, Iowa City, Iowa
C.-J. Richard Shi  Department of Electrical and Computer Engineering, University of Iowa, Iowa City, Iowa
Sponsors
EDAC : Electronic Design Automation Consortium
IEEE-CAS : Circuits & Systems
SIGDA: ACM Special Interest Group on Design Automation
Publisher
ACM  New York, NY, USA
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ABSTRACT

Fault-driven analog and mixed-signal testing calls for rapid fault simulationtechniques. A problem that has not been addressed effectivelyby existing research is that circuit parameters have tolerance ranges.In this paper, we propose representing parameters under variations asintervals, and present an efficient algorithm - based on interval analysisand Householder's formula - to compute the worst-case responsebounds of good and faulty linear(ized) circuits under parameter variations.Our approach takes CPU time comparable to one nominal circuitsimulation, and always produces correct and conservative results. Thealgorithm has been implemented into SPICE3F5. Experimental resultsshow an acceptable accuracy.


REFERENCES

Note: OCR errors may be found in this Reference List extracted from the full text article. ACM has opted to expose the complete List rather than only correct and linked references.

 
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Michael W. Tian: colleagues
C.-J. Richard Shi: colleagues

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